본문 바로가기 주메뉴 바로가기
22대 대한민국 국회 국회정보길라잡이 국회의원검색
회원가입 로그인
HOME

정보검색

소장정보 검색

국회도서관 홈으로 정보검색 소장정보 검색
결과 내 검색 동의어 포함
결과 내 검색 동의어 포함

-

초록보기

The closed-loop neural interface is an actively researched field with broad applications. However, it has a serious issue in that stimulation itself makes huge artifacts (~mV) in the recording system saturating the amplifier, contaminating bio-signal (~ 50𝛍V) and the post-analysis during a disturbed period. Several stimulation artifact removal (SAR) techniques were presented but have trade-offs between conversion time and algorithm accuracy. Here, we suggested a closed-loop neural interface with a fast convergence SAR algorithm while sustaining adequate removal accuracy. The amplifier-free ADC-direct 2nd-order continuous delta-sigma modulator recording stage is adopted to provide ~15𝛍 Vrms input-referred integrated noise from 5Hz to 5kHz which is adequate to record bio-signal. Also, it succeeds in recording ~10mV signals about the size of the stimulation artifact. The fast-convergence SAR module provides stable accuracy under the versatile recording environment. The chip is designed using the TSMC 65-nm CMOS process. The chip is composed of 18 input channels, 2 SAR blocks, one stimulation channel, and 2 CIC filters for down-sampling. The entire chip area is 1mm².

권호기사

권호기사 목록 테이블로 기사명, 저자명, 페이지, 원문, 기사목차 순으로 되어있습니다.
기사명 저자명 페이지 원문 목차
(A) 28-GHz CMOS power amplifier with ribbon cell Younseok Han, Seungchan Lee, Dong-Ho Lee, Gwanghyeon Jeong p. [1-6]

CNN inference accelerator optimized for AI applications for object detection Bogeun Jung, Wooyoung Park, Hyungwon Kim p. [1-6]

Performance improvement analysis of fNIRS IC Bumjun Koh, Kyeongha Kwon, Hyeon-Min Bae p. [1-9]

(An) optoelectronic read-out IC for indoor-monitoring LiDAR sensors in 180-nm CMOS Shinhae Choi, Yeojin Chon, Sung Min Park p. [1-5]

(A) 28-GHz down-converter for 5G direct-conversion receivers in 65-nm CMOS technology Jinman Myung, Geonwoo Park, Ho Kim, Youngseok Kwak, Ilku Nam p. [1-5]

(The) closed-loop neural interface available simultaneously recording and stimulation using fast convergence stimulation artifact removal Geunchang Seong, Jaeouk Cho, Hee Young Jung, Chul Kim p. [1-6]

Design study of a 240-GHz amplifier frequency doubler chain based on SiGe BiCMOS technology Giyeong Nam, Wooyong Keum, Jae-Sung Rieh p. [1-5]

(A) V-band CMOS frequency doubler in 65 nm CMOS In Cheol Yoo, Dong Ouk Cho, Chul Woo Byeon p. [1-5]

추천서가 (다양한 추천 자료를 만나보세요)

권호기사보기

권호기사 목록 테이블로 기사명, 저자명, 페이지, 원문, 기사목차 순으로 되어있습니다.
기사명 저자명 페이지 원문 기사목차