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22대 대한민국 국회 국회정보길라잡이 국회의원검색
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초록보기

This work presents a design methodology of a low-noise and low-power continuous-time delta-sigma modulator (CT DSM) architecture for bio-signal acquisition. Along with the 2nd-order CT loop filter architecture, a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is used as a quantizer to achieve power efficiency. The incremental operation is added to enable multi-channel processing. Designed and fabricated in a 180nm CMOS process, the proposed architecture achieves 80.1dB SNDR in a 250kHz bandwidth (BW) under a 1.8V supply. With a power consumption of 2mW, the proposed architecture has a Schreier Figure of Merit (FoMS) of 161dB.

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기사명 저자명 페이지 원문 목차
Design of power management integrate circuit implemented at the active EMI filter Sangyeong Jeong, Jingook Kim p. [1-6]

(A) low power mixed signal convolutional neural network for deep learning SoC Malik Summair Asghar, Syed Asmat Ali Shah, Hyung Won Kim p. [1-6]

Blood glucose monitoring and communicative implantable chip using a wireless power transfer Hyeonkeon Lee, Honghyeon Park, Sanghoek Kim p. [1-7]

D-band high gain and wide bandwidth power amplifier design in 65nm CMOS adopting dual-peak Gmax technique Hyo-Ryeong Jeon, Sang-Gug Lee p. [1-5]

Ultra-wideband pulse generator with simultaneous optimization of sidelobe suppression and essential bandwidth Hafiz Usman Mahmood, Jusung Kim, Sang-Gug Lee p. [1-6]

(A) low-ripple charge pump based on a parallelized ring oscillator with latches Woo Jin Jang, Yeon Jae Shin, Jung Hyup Lee p. [1-6]

Design of a continuous-time delta-sigma modulator for bio-signal acquisition Ye-Dam Kim, Seung-Tak Ryu p. [1-6]

9-bit 500-MS/s pipelined SAR ADC using dynamic amplifier with background calibration Soohoon Lee, Hyeonsik Kim, Jintae Kim p. [1-7]

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