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22대 대한민국 국회 국회정보길라잡이 국회의원검색
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This paper presents a K-band CMOS harmonic response rectifier based on 2-stage cross coupled bridge rectifier. The proposed CMOS harmonic response rectifier configured with rectification stage and second harmonic output stage can be used for nonlinear detection based wireless power transfer. The transformer in the rectification stage did not only generate differential signal but also matched to 50 Ω at a fundamental frequency to achieve low transmission loss for high power conversion efficiency (PCE) and conversion gain (CG). To maximize CG, the second harmonic stage was matched to 50 Ω at second harmonic frequency. The proposed CMOS harmonic response rectifier was designed using a 65 nm CMOS process and had a chip area of 0.35 mm x 0.22 mm. The simulation results show that the PCE was 15.2–20.2 %, and the CG was -23–-21.2 dB at an input power of 25.5 dBm in the frequency range of 20.5–27 GHz.

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