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22대 대한민국 국회 국회정보길라잡이 국회의원검색
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초록보기

This work presents a low-jitter ring-oscillator-based digital PLL (RO-DPLL). To achieve low jitter, the proposed RO-DPLL used calibration techniques to optimize the gain of the Proportional-path (P-path) and Integral-path (I-path) in the digital-loop-filter (DLF) simultaneously. Since the effect of flicker noise increases as the frequency increases, the frequency drift of the RO-DPLL becomes more severe in the operation of the RO-DPLL. Thus, it is critical to calibrate the gain of the I-path to an optimal value because I-path of DLF compensates for the frequency error of the PLL. Moreover, the optimally-spaced time-to-digital-converter (OS-TDC) with the threshold calibrator provides sufficient information, supporting the efficient operation of the calibrators. Due to the use of the P/I-path co-optimization (PICO) and OS-TDC with calibrator, the proposed RO-DPLL achieved the rms jitter of 343 fs and the reference spur of –65dBc. And, its FoMjitter,N was –258.5 dBc, comparable to the state-of-the-art RO-based analog PLLs.

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(An) energy-efficient Buck-Boost converter for mobile applications Sunghae Kim, Jaeduk Han p. [1-5]

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