This paper presents a 9-bit 4-stage pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC) using a dynamic amplifier with a background inter-stage gain calibration technique, which resolves the capacitor digital-to-analog converter (CDAC) mismatch of the first stage and the gain errors caused by process, voltage, and temperature (PVT) variations. The increase of residue voltage caused by the two paired offset comparators used for calibration is reduced by the dither injection of the 1st-stage CDAC. The ADC is designed as 3b+3b+3b+3b for each stage and has 3-bit redundancy. The proposed ADC in this paper is fabricated in a 28 nm CMOS process, occupies an area of approximately 0.02 mm², and only consumes 11 mW of power. Furthermore, the SNDR of the ADC is 48.37 dB when measured at a sampling rate of 241.37 MHz, which is the Nyquist rate for this ADC.