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22대 대한민국 국회 국회정보길라잡이 국회의원검색
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This paper presents a 9-bit 4-stage pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC) using a dynamic amplifier with a background inter-stage gain calibration technique, which resolves the capacitor digital-to-analog converter (CDAC) mismatch of the first stage and the gain errors caused by process, voltage, and temperature (PVT) variations. The increase of residue voltage caused by the two paired offset comparators used for calibration is reduced by the dither injection of the 1st-stage CDAC. The ADC is designed as 3b+3b+3b+3b for each stage and has 3-bit redundancy. The proposed ADC in this paper is fabricated in a 28 nm CMOS process, occupies an area of approximately 0.02 mm², and only consumes 11 mW of power. Furthermore, the SNDR of the ADC is 48.37 dB when measured at a sampling rate of 241.37 MHz, which is the Nyquist rate for this ADC.

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D-band high gain and wide bandwidth power amplifier design in 65nm CMOS adopting dual-peak Gmax technique Hyo-Ryeong Jeon, Sang-Gug Lee p. [1-5]

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9-bit 500-MS/s pipelined SAR ADC using dynamic amplifier with background calibration Soohoon Lee, Hyeonsik Kim, Jintae Kim p. [1-7]

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