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Flip-Flop (FF) is the basic block of sequential digital circuits, which has a significant impact on the speed, power, and stability of digital systems. Reducing the power consumption of FFs is an attractive solution for attaining good energy efficiency of digital systems. However, the conventional TGFF (Transmission-gate flip-flop) consumes excessive dynamic power at clock inverters even though the data transition does not occur. To eliminate redundant clock transitions, some techniques are applied. This paper analyzes and compares recently published low-power FFs in 65 nm CMOS.

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기사명 저자명 페이지 원문 목차
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(A) 10 Gbps optical receiver analog front-end and MZM driver in 65nm CMOS Abdul Qahir, Sang Gug Lee p. [1-6]

(A) wideband 60 GHz Gm-boosted up-conversion mixer Cheol So, Song Cheol Hong p. [1-6]

(An) evaluation and comparison of state-of-the-art flip-flops for low-power applications Kyoung Hun Kang, Wan Yeong Jung p. [1-5]

Analysis of the TEG maximum power point tracking operation with continuously scalable-conversion-ratio SC converter Hyun Jin Kim, Chul Woo Kim p. [1-5]

Counter-based frequency discriminator for fine dust sensor Suneui Park, Han Gi Park, Ju Yeop Kim, Joo Eun Bang, Yu Hwan Shin, Jae Hyouk Choi p. [1-5]

Design of InP HBT 230-GHz frequency multiplier chain with a multiplication factor of 18 Sang Ki Min, Woo Yong Keum, Hee Kang Son, Jung Hwan Yoo, Do Yoon Kim, Jae Sung Rieh p. [1-6]

(A) leakage-tolerant 4.58µJ·ppm2-FoMs reconfigurable RC-to-digital converter for multi-sensor readout Dong Wook Kim, Ho Yeong Han, Jung Hyup Lee p. [1-6]

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