Flip-Flop (FF) is the basic block of sequential digital circuits, which has a significant impact on the speed, power, and stability of digital systems. Reducing the power consumption of FFs is an attractive solution for attaining good energy efficiency of digital systems. However, the conventional TGFF (Transmission-gate flip-flop) consumes excessive dynamic power at clock inverters even though the data transition does not occur. To eliminate redundant clock transitions, some techniques are applied. This paper analyzes and compares recently published low-power FFs in 65 nm CMOS.