Title Page
Contents
Abstract 10
Chapter 1. Introduction 12
1.1. Background and Motivation 12
1.2. Overview of Wireless Power Transfer System 13
1.3. Challenges 18
1.4. Thesis Organization 19
Chapter 2. Prior work 21
2.1. Rectifier 21
2.2. DC-DC Converter 23
2.3. Summary 25
Chapter 3. Dual-Mode Active Rectifier with Gate Charge Recycled Technique and Step-down DC-DC Converter 26
3.1. Proposed Dual-Mode Active Rectifier 29
3.1.1. Matching Network 32
3.1.2. Open Loop Delay Circuit (OLDC) 33
3.1.3. Zero Current Sensing Circuit 38
3.1.4. Gate Charge Recycled Technique 40
3.2. Step-up DC-DC Converter 44
3.2.1. Measurement Results 50
3.2.2. Summary 58
Chapter 4. Low Frequency EM Rectifier with Passive AC-DC Voltage Quadrupler and Step-up DC-DC Converter 59
4.1. System Architecture 62
4.2. Rectifier with Unbalance Comparators 62
4.3. Step-up DC-DC Converter 68
4.4. Measurement Results 75
4.5. Summary 79
Chapter 5. Conclusion 80
References 81
Table 1.1. Characteristics of inductive coupling method, magnetic resonance and RF method. 13
Table 3.1. Power Consumption Analysis of Rectifier 43
Table 3.2. Performance Parameter of DC-DC Converter 48
Table 3.3. Comparison Table with Prior Work 56
Table 4.1. Power Conversion Analysis of EM Rectifier 67
Table 4.2. Results of Soft-Start Circuit 70
Table 4.3. Performance Parameter of DC-DC Converter 72
Table 4.4. Performance Comparison with Prior Works 79
Fig. 1.1. Conceptual diagrams of (a) WPT Transmitter system, (b) WPT Receiver system 15
Fig. 1.2. Conceptual diagrams of RF Wireless Power Transmitter and Receiver system 16
Fig. 1.3. Proposed Block diagram of WPT System 17
Fig. 3.1. Block diagram of Dual-Mode Active rectifier 32
Fig. 3.2. Block diagram of Matching Network 33
Fig. 3.3. Block diagram of open-loop delay circuit (OLDC) 35
Fig. 3.4. Timing diagram of Open Loop Delay Circuit (OLDC) 37
Fig. 3.5. Simulation result of Core and Fine delay 37
Fig. 3.6. Zero Current Sensing (ZCS) Circuit 38
Fig. 3.7. Simulation result of Zero Current Sensing (ZCS) Circuit 39
Fig. 3.8. Timing diagram of Zero Current Sensing (ZCS) Circuit 40
Fig. 3.9. Gate Charge Recycling Circuit 41
Fig. 3.10. Simulation result of charge recycling circuit 43
Fig. 3.11. Step down DC-DC Converter 45
Fig. 3.12. Dynamic pull-up resistor gate driver (b) Multiple series Inverter 45
Fig. 3.13. Inductor current path during dead time 47
Fig. 3.14. Circuit diagram of saw-tooth generator 48
Fig. 3.15. Circuit diagram of Max Generator 49
Fig. 3.16. Measurement Set-up for PMIC 50
Fig. 3.17. Microphotography of the proposed chip 51
Fig. 3.18. Measurement result of WPC mode active rectifier 51
Fig. 3.19. Measurement result of A4WP mode active rectifier 52
Fig. 3.20. Measurement PCE of WPC and A4WP mode active rectifier with and without gate charge recycled technique 53
Fig. 3.21. Measured result of DC-DC Converter 53
Fig. 3.22. Measured result of Dynamic pull-up resistor gate driver 54
Fig. 3.23. Measured power efficiency of DC-DC Converter 54
Fig. 4.1. Block diagram of Electromagnetic Energy Harvesting System 61
Fig. 4.2. Block diagram of the EM Rectifier 63
Fig. 4.3. Timing diagram of EM Rectifier 65
Fig. 4.4. Unbalance-size comparator with NMOS input transistor 65
Fig. 4.5. Unbalance-size comparator with PMOS input transistor 66
Fig. 4.6. Delay and offset of unbalance-size comparator 66
Fig. 4.7. Simulation result of EM rectifier 67
Fig. 4.8. Block diagram of DC-DC Converter 69
Fig. 4.9. Soft Start-up Circuit 70
Fig. 4.10. Saw-tooth generator 72
Fig. 4.11. Max duty generator 73
Fig. 4.12. Simulation result of min-max generator 74
Fig. 4.13. Simulation result of DC-DC Converter 74
Fig. 4.14. Measurement Setup 75
Fig. 4.15. Microphotograph of the proposed chip 76
Fig. 4.16. Measured efficiency of EM rectifier versus input frequency at 0.6 V input peak voltage 77
Fig. 4.17. Measured efficiency of EM rectifier versus load current 77
Fig. 4.18. Measured efficiency of DC-DC converter versus load current 78
Fig. 4.19. Measured result of overall system 78