Title Page
ABSTRACT
국문 초록
Contents
CHAPTER 1. INTRODUCTION 13
1.1. Backgrounds 13
1.2. Thesis overview 13
CHAPTER 2. DATA EDGE SAMPLING TECHNIQUE 17
CHAPTER 3. CIRCUIT IMPLEMENTATION 20
3.1. Top block diagram 20
3.2. High-pass filter 22
3.3. Time-based transition detector (TBTD) 26
3.4. Decoder 29
CHAPTER 4. MEASUREMENT RESULTS 31
CHAPTER 5. CONCLUSION 37
REFERENCES 38
Table 1. Truth table for decoder 30
Table 2. Performance summary and comparison with the prior works of single-ended NRZ receiver. 36
Figure 1.1. Trend of clock frequency in memory interfaces. 15
Figure 1.2. (a) Conventional and (b) proposed data sampling method in half-rate architecture. 16
Figure 2.1. (a) Ideal waveforms and vertical margins of the input and output of the HPF and (b) the outputs of two comparators whether the data transition occurs or not. 19
Figure 3.1. RX top block diagram. 20
Figure 3.2. (a) Conventional passive high-pass filter, (b) proposed high-pass filter and (c) its input and output eye diagrams. 22
Figure 3.3. Schematic of the front-end of the proposed RX. 25
Figure 3.4. Monte-Carlo simulation results of (a) CKSAMP to CKDEL and (b) BUF1 delays.[이미지참조] 25
Figure 3.5. Schematic of TBTD and its timing diagram. 27
Figure 3.6. Simulation results of (a) TBTD offset and (b) worst case of Δtmar across the PVT variations.[이미지참조] 28
Figure 3.7. Decoder consists of 4:2 MUX. 29
Figure 4.1. Chip micrograph. 31
Figure 4.2. Measurement setup. 31
Figure 4.3. The frequency response of 31-inch ISI channel and the eye diagram after the channel. 33
Figure 4.4. Measurement results of (a) BER bathtub curve and (b) power breakdown. 34