Title Page
Contents
ABSTRACT 10
초록 11
CHAPTER 1. INTRODUCTION 12
CHAPTER 2. DEVICE CHARACTERIZATIONS OF J-MISFET 16
2.1. Device Structure Engineering 16
2.2. Device Operating Mechanisms 19
2.2.1. JFET/MISFET Single-gate Operations 19
2.2.2. J-MISFET Heterogeneous Dual-gate Operations 20
CHAPTER 3. ELECTRICAL CHARACTERISTICS OF J-MISFET 22
3.1. J-MISFET Electrical Characteristics 22
3.2. Analysis of Electrical Properties by MoS₂ Channel Thickness 26
CHAPTER 4. LOGIC OPERATIONS 34
4.1. Resistive Load Inverter for JFET/MISFET/J-MISFET 34
4.2. Selective Logic gate behaviors (NOR/NAND) of J-MISFET 35
CHAPTER 5. PHOTO-RESPONSE 39
5.1. Static and Dynamic Photo-Response of J-MISFET 39
5.2. Comparison of Photo-Response between JFET/MISFET/J-MISFET 41
CHAPTER 6. ADVANCED APPLICATIONS - COMBINATION OF LOGIC AND PHOTO-RESPONSE 44
6.1. Logic Operation under Light Illumination 44
6.2. Application in Practical Transmission Model based on PCM System 47
CHAPTER 7. CONCLUSIONS 53
EXTRA CHAPTER. EXPERIMENTAL SECTION 54
E.1. Device Fabrication 54
E.2. Electrical Characterizations 54
REFERENCES 56
Figure 1.1. (a) Short channel effect. (b) Molybdenum disulfide (MoS₂) based field-effect transistor (FET) with (i) 1-nm gate lengths (ii) sub-1-nm gate lengths (c)... 12
Figure 1.2. (a) Metal-Insulator-Semiconductor field-effect transistor (MISFET) (b) Junction field-effect transistor (JFET) with 2D TMDCs. 13
Figure 2.1. D evice structure of our p-WSec₂/n-MoS₂ heterojunction JFET. (a) 3D schematic. (b) Top view schematic. 16
Figure 2.2. JFET structure optimization process. Before (a,b,c) / After (d,e,f) the graphene JFET gate electrode vertically covers the junction area. (a,d) Top view... 17
Figure 2.3. (a) PN diode components (gate-source and gate-drain side) in JFET. (b) Diode curves in both log and linear scale. 17
Figure 2.4. (a) Proposed circuit symbol (b) 3D schematic (c) OM image and (d) Top view schematic of J-MISFET. 18
Figure 2.5. Working mechanisms of MISFET. (a) ON state (VG〉0), carrier accumulation. (b) OFF state (VG 〈0), carrier depletion. Working mechanisms of JFET. (c) ON...[이미지참조] 19
Figure 2.6. Working mechanisms of J-MISFET (a) ON state (VG〉0). (b) OFF state (VG 〈0).[이미지참조] 20
Figure 2.7. Energy band diagram of ON state (VG〉0) and OFF state (VG 〈0) for (a) JFET (ON-channel opening/OFF-channel blocking). (b) MISFET and MoS₂-Graphene...[이미지참조] 21
Figure 3.1. (a) Schematic of gate connection for each gate operation (i. JFET, ii. MISFET, and iii. J-MISFET). (b) Transfer characteristics for JFET/MISFET/J-MISFET,... 22
Figure 3.2. Output characteristics of (a) JFET (b) MISFET (c) J-MISFET (d) the magnified J-MIS output. 24
Figure 3.3. (a) SS curves as a function of drain current (ID). (b) Effective mobility of J-MISFET at various drain voltages (VD).[이미지참조] 25
Figure 3.4. Effective mobility calculation of J-MISFET. (Split C-V method) 26
Figure 3.5. JFET and J-MSIFET transfer characteristics for various MoS₂ channel thickness (a) thin ~6nm. (b) medium ~12nm. (c) thick ~22nm. 26
Figure 3.6. OM image and MoS 2 channel AFM data of (a) Fig. 3.5a (~6nm). (b) Fig. 3.5b (~12nm). (c) Fig. 3.5c (~22nm). 27
Figure 3.7. Transfer curves with gate leakage current (IG) of JFET and JMISFET in full range (up panel, a-c) and in the same y-scale as Fig. 3.5 (down panel, d-e)....[이미지참조] 27
Figure 3.8. Side view channel schematics of thin and thick channel devices working with JFET single-gate or J-MISFET dual-gate in OFF state (VG〈0).[이미지참조] 29
Figure 3.9. Pinch-off voltage (VP) extraction for (a) Fig. 3.5a (b) Fig. 3.5b (c) Fig. 3.5c. (d) Comparison for pinch-off voltage with previous work for junction devices.[이미지참조] 30
Figure 3.10. Comparison for SS characteristics with previous work. 31
Figure 3.11. OM images and MoS₂ channel AFM data of our devices in Fig. 3.10. 32
Figure 3.12. (a) OM image and AFM data (b) Transfer characteristics of JFET and J-MISFET in ~50nm MoS₂ channel device. 33
Figure 4.1. Resistive load inverter VTC curves and extracted gain values for each gate (JFET, MISFET, and J-MISFET). Inset shows measurement circuit diagrams. 34
Figure 4.2. (a) 2D contour color map for drain current (ID) (b) transfer characteristics at each JFET/MISFET gate bias in the range from -0.8 to 0.4V. 3D color map...[이미지참조] 35
Figure 4.3. (a) NOR logic VTC. VMISFET is swept from -0.35 to 0.15V with a fixed VJFET of -0.35V (black line) and 0.15V (red line). (b) VOUT characteristics for NOR...[이미지참조] 37
Figure 5.1. (a) Photo-induced static transfer characteristics of J-MISFET under dark, light illumination, and redark conditions. J-MSIFET transfer curves with gate leakage... 39
Figure 5.2. J-MISFET dynamic photo-switching behaviors with LED on/off frequency of (a) 1Hz, (b) 100 Hz, (c) 500 Hz, and (d) 1k Hz under both J-MIS gate (VG) and...[이미지참조] 40
Figure 5.3. Responsivity for each gate (JFET/MISFET/J-MISFET) under the same light conditions (520nm LED, 0.32 mW/cm²) and the same device. 41
Figure 5.4. Photo-induced static transfer characteristics of (a) JFET and (b) MISFET single-gate under dark, light illumination, and redark conditions. 42
Figure 5.5. Photo-induced static transfer characteristics of J-MISFET under (a) red (660nm) (b) green (520nm) (c) blue (465nm) (d) UV (385nm). 43
Figure 6.1. Photo-inverter application (Photo+logic) with J-MISFET. (a) Photo-induced static transfer characteristic of J-MIS. (b) Dynamic photoswitching behavior with the... 44
Figure 6.2. (a) Transfer characteristics of JFFT. The JFET gate is swept from -0.6 to 0.5V under a fixed MISFET gate bias at -0.4V and 0.4V with dark and light... 45
Figure 6.3. Conceptualized illustration of J-MISFET applications which combine the logic and photo-response. 46
Figure 6.4. Conventional PCM transmission system block diagram. 47
Figure 6.5. (a) Block diagram and (b) Detailed process of the transmitter section. (c) Synchronization between the key-encoded signal in the time domain. (d) 2:1... 48
Figure 6.6. (a) Block diagram of a PCM-based transmission model in our work. (b) The original analog input signal and key (light) signal. (c) Detailed demodulation... 49
Figure 6.7. Demodulated output voltage (VOUT) from J-MISFET (a) using the correct key (same as Fig. 6.6b key signal). (b) using the wrong key with 180˚ phase shift.... 50
Figure 6.8. Demodulated analog signal according to key (light) signal under the same JFET and MISFET input signal. (a) correct key (b) 180˚ phase shift (c) 1-bit error... 52