Title Page
Contents
초록 13
Abstract 14
Chapter 1. Introduction 15
1.1. Introduction of NAND flash memory 15
1.2. Effects of multi-finger gate high-voltage (HV) MOSFETs 17
1.3. Degradation factors of multi-finger gate MOSFETs 20
Chapter 2. Simulation setup 24
Chapter 3. Results and discussion 27
3.1. Effects of channel width effect 27
3.2. Effects of increasing the number of fingers 32
Chapter 4. Compact Modeling of the Snapback Region 40
4.1. Basic mechanism of High-Voltage MOSFET 40
4.2. Snapback Curve Extraction 42
Chapter 5. Conclusion 45
Reference 46
Table. Ⅰ. Design parameters of 2D multi-finger gate MOSFETs and 3D MOSFETs 26
Fig. 1. Scaling trend of the NAND flash memory. 16
Fig. 2. Top view of an interdigitated configuration of multi-finger gate MOSFETs varying transistor finger width (Wf) versus the number of fingers (nf).[이미지참조] 18
Fig. 3. Effective area variation and reduction of area versus the number of fingers. 19
Fig. 4. Cross-section of an NMOS transistor showing parasitic BJT. 22
Fig. 5. Hole current density in the (a) shared drain and (b) source structure. 22
Fig. 6. (a) Measured substrate currents at breakdown for different channel lengths and widths [13]. (b) Measured substrate currents at breakdown for different widths of... 23
Fig. 7. Simulated model of 2D multi (N=2,3,4…)-finger gate MOSFET structure. 25
Fig. 8. Simulated model of 3D bulk MOSFETs with horizontal view (x-y plane) of a simulated model. 25
Fig. 9. The distribution of substrate hole current density at the horizontal view (z-x plane) of simulated model with various channel width. 29
Fig. 10. (a) Hole current density, (b) substrate electrostatic potential at the cross-sectional view of A-A' at Fig. 9 (cross-section of 1.0 μm below the oxide/channel interface). 30
Fig. 11. (a) Simulated substrate maximum potential and snapback breakdown voltage (SNBV) with various channel width to exclude channel width effect in high bias... 31
Fig. 12. Hole current density contour of two-finger gate MOSFETs (a) with a shared drain structure and (b) with a shared source structure. (c) Simulated ID-VD characteristics of two-...[이미지참조] 34
Fig. 13. (a) Hole current density contour of four-finger gate MOSFETs with different source/drain configuration. (b) Simulated ID-VD characteristics of four-finger gate...[이미지참조] 35
Fig. 14. (a) Hole current density and (b) impact ionization contour of 3, 4, 5-finger gate structure with VG=2.3 V, VD=15 V.[이미지참조] 37
Fig. 15. Simulated lattice temperature in channel with various finger gate structure. 38
Fig. 16. Output curve of simulated 3, 4, 5-finger gate structure with VG=2.3 V[이미지참조] 39
Fig. 17. I-V characteristics of MOSFET with L=1 μm, W=1 μm, Vₜₕ=0.6 V simulated by Nanospice simulation. 41
Fig. 18. (a) Schematic diagram of a n-channel MOSFET including parasitic BJT (b) equivalent circuit incorporating MOSFET with parasitic BJT behavior and (c) spice model... 43
Fig. 19. I-V curve of MOSFET (a) using TCAD simulation and (b) using NanoSpice. 44