표제지
국문초록
목차
제1장 서론 13
제1절 동기 13
제2절 논문 구성 15
제2장 배경 이론 16
제1절 Single-bit pulse response 16
제2절 송신기의 구조와 동작 17
제3절 Equalization 기법 18
1. Feed-Forward Equalizer 18
2. Continuous-Time Linear Equalizer 22
3. Decision Feedback Equalizer 23
제4절 SS-LMS 알고리즘 25
제3장 제안하는 수신기 27
제1절 수신기의 구조와 동작 27
제2절 CTLE의 설계 29
제4장 제안하는 Equalizer의 Adaptation 알고리즘 42
제1절 중첩의 원리를 적용한 CTLE의 Adaptation 알고리즘 42
제2절 PRBS에서의 Equalizer Adaptation 알고리즘 51
제3절 Data Level Adaptation 53
제4절 DFE Adaptation 55
제5장 시뮬레이션 결과 57
제1절 CTLE Schematic 시뮬레이션 57
제2절 Adaptation 시뮬레이션 63
제6장 결론 66
참고문헌 67
ABSTRACTS 68
Table 2.1. Matrix form representation for 3-Tap Feed-forward equalizer 20
Table 4.1. Adaptation algorithm for T-level and CTLE boost 49
Figure 2.1. Single bit pulse response with (a) Pre-cursor, main-cursor, and post-cursors of channel. (b) Discrete-time... 16
Figure 2.2. Transmitter architecture 17
Figure 2.3. Pulse sequence according to Feed-Forward Equalizer 18
Figure 2.4. Eye diagram (a) without FFE (b) with FFE 21
Figure 2.5. Frequency response of TX FFE(FIR) 21
Figure 2.6. Frequency response of continuous-time linear equalizer 23
Figure 2.7. A feedback loop canceling the first post-cursor. 24
Figure 3.1. Receiver architecture 28
Figure 3.2. Schematic of conventional CTLE 29
Figure 3.3. Half circuit representation of CTLE 30
Figure 3.4. Simulated frequency response of conventional CTLE 31
Figure 3.5. Block representation of transconductance-transimpedance CTLE 32
Figure 3.6. Half circuit representation of (a) Gm stage (b) TIA stage 33
Figure 3.7. Small signal representation of current-mode TIA 34
Figure 3.8. Two path of Gm stage (a) 1st path (b) 2nd path[이미지참조] 35
Figure 3.9. Frequency response according to (a) path (b) overall 36
Figure 3.10. Schematic of proposed CTLE (a) Gm stage (b) TIA stage. 36
Figure 3.11. An effect caused by bandwidth limitation of common mode feedback loop. 38
Figure 3.12. Common mode feedback for Gm stage and replica biasing for transimpedance amplifier 39
Figure 4.1. Method that compares and matches the amount of high and low frequency. 43
Figure 4.2. Situation where the magnitude of long-tail ISIs have increased. 44
Figure 4.3. (a) Single bit pulse response after CTLE. (b) Single bit pulse response after CTLE and DFE 45
Figure 4.4. Single bit pulse response according to the change of CTLE boost code. 45
Figure 4.5. (a)Training Sequence for equalizer (b)Discrete time representation of single bit pulse response when ISI exists only... 46
Figure 4.6. Superposition of single bit pulse over time 48
Figure 4.7. Situation that DLV coefficients (a)Dn is generated. (b) Up is generated. 53
Figure 4.8. Situation that DFE coefficients Up is generated. 56
Figure 4.9. Situation that DFE coefficients Down is generated. 56
Figure 5.1. Linearity characteristic of CTLE 57
Figure 5.2. Comparison of simulated frequency response of conventional CTLE and proposed CTLE according to (a) Cs and... 58
Figure 5.3. Resistance of Rs according to Rs code 60
Figure 5.4. Simulated frequency of proposed CTLE when (a) Rz / (b) Cz / (c) RFB / (d) bias current of Gm stage is changed 60
Figure 5.5. ISI amplitude when CTLE Boost code is changed. 63
Figure 5.6. Eye-diagram after adaptation of equalizer (a) NRZ Receiver Input (b) NRZ CTLE output (c) NRZ DFE output (d)... 65