Title Page
Abstract
Contents
Introduction 13
1. DifuzzRTL : Differential Fuzz Testing to Find CPU Bugs 18
1.1. Introduction 18
1.2. Background 22
1.2.1. CPU Development and Testing 22
1.2.2. Fuzzing 25
1.3. Motivation 27
1.3.1. Coverage Definition for RTL Fuzzing 28
1.3.2. Input Space for RTL Fuzzing 33
1.4. Design 34
1.4.1. SimInput Mutation 36
1.4.2. ISA Simulation 39
1.4.3. RTL Compilation with Register Coverage 40
1.4.4. RTL Simulation 44
1.4.5. Checking Execution Results 46
1.5. Implementation 47
1.5.1. RTL Compiler Pass for Register-coverage Instrumentation 47
1.5.2. CPU Fuzzing Framework 47
1.6. Evaluation 48
1.6.1. Evaluation Setup 49
1.6.2. Fuzzing Synthetic RTL 51
1.6.3. Fuzzing Real-World Designs (Software Simulation) 54
1.6.4. Fuzzing Real-World Designs (FPGA Emulation) 59
1.6.5. Newly Discovered Bugs in Real World RTL Designs 61
1.6.6. Case Study with Real-World Bugs 63
1.7. Limitation 65
1.8. Related Work 66
1.9. Conclusion 68
2. SpecDoctor: Differential Fuzz Testing to Find Transient Execution Vulnerabilities 70
2.1. Introduction 70
2.2. Background 74
2.2.1. Transient Execution Attacks 74
2.2.2. CPU Microarchitecture 76
2.2.3. Fuzzing 78
2.3. Challenges in SpecDoctor 79
2.4. Design of SpecDoctor 82
2.4.1. Phase 1: Attack Configuration 83
2.4.2. Phase 2: Triggering Transient Execution 85
2.4.3. Phase 3: Accessing and Transmitting Secret 88
2.4.4. Phase 4: Receiving Secret 94
2.5. Implementation 95
2.6. Evaluation 96
2.6.1. Evaluation Setup 96
2.6.2. Triggering Transient Execution 97
2.6.3. Finding Potential Side-Channels 99
2.6.4. Multi-phased Fuzzing 101
2.6.5. Found Transient Execution Vulnerabilities 102
2.7. Findings of SpecDoctor 104
2.7.1. Boombard on RISC-V Boom 104
2.7.2. Birgus on RISC-V NutShell 107
2.8. Discussions 110
2.9. Related Work 112
2.10. Conclusion 114
3. FairLearning : Protecting Training Data from Untrusted Machine Learners 116
3.1. Introduction 116
3.2. Background 119
3.2.1. Deep Learning 119
3.2.2. Data Reconstruction Attacks in Machine Learning 121
3.2.3. Confidential Computing 122
3.3. Motivation 123
3.3.1. Threat Model 123
3.3.2. Limitations of Existing Approaches & Related Work 125
3.4. Theoretical Building Blocks 128
3.4.1. Problem and Challenge 128
3.4.2. Our Solution: FairFunction 130
3.5. Design of FairLearning 139
3.5.1. Restricting Control and Data Flows with FairSandbox 141
3.5.2. Checking Model Fairness with FairOracle 142
3.6. Implementation 144
3.7. Evaluation 148
3.7.1. Security Enhancement of FairLearning 149
3.7.2. Performance Effect of FairLearning 157
3.8. Discussion 158
3.9. Conclusion 161
Conclusion 162
Bibliography 163
초록 188
Table 1.1. Coverage instrumentation overheads for synthetic RTL designs. 52
Table 1.2. p-values of the Mann-Whitney U test between distributions, where each distribution is populated with each... 53
Table 1.3. The results of Vargha Delaney's A12 measure between the distributions. The coverage-guiding method name... 53
Table 1.4. Instrumentation overhead for real-world CPU RTLs. 55
Table 1.5. Runtime overheads of register-coverage and mux-coverage for real-world CPU RTLs. 55
Table 1.6. Runtime overheads of register-coverage and mux-coverage for FPGA emulation. The numbers in the brackets... 59
Table 1.7. A list of newly discovered bugs by DifuzzRTL. DifuzzRTL identified 16 bugs in total, all of those were confirmed by respective... 61
Table 1.8. Average time to find real-world bugs using each approach. 63
Table 2.1. Transient executions in RISC-V Boom and NutShell discovered by SpecDoctor phase 2. rr: RoB rollback... 97
Table 2.2. Timing-change coponents found by SpecDoctor in both RISC-V Boom and NutShell. The table partially shows... 98
Table 2.3. Static and dynamic overheads of SpecDoctor. Numbers in paranthesis show the overheads against the original. 100
Table 2.4. Comparison study of finding transient execution vulnerabilities. All the attacks have accessed secret through a load instruction. 101
Table 2.5. Variants of transient execution vulnerabilities found by SpecDoctor. 102
Table 2.6. Comparison of SpecDoctor versus related works. 113
Table 3.1. Evaluation tasks and datasets for each task. 150
Table 3.2. Specification of the trained target models and the evaluation model for image classification. 152
Table 3.3. BWleakage achieved in each scenario of image classification task. BWleakage of the attacks not possible in each scenario is set 0. All... 154
Table 3.4. Model specification for image segmentation task. 155
Table 3.5. Achieved BWleakage in image segmentation task. 155
Figure 1.1. Framework of ISA simulation and RTL simulation. RTL simulation requires SoC to run CPU RTL designs with an executable file. 24
Figure 1.2. A general workflow of coverage-guided fuzzing techniques 26
Figure 1.3. Two independent FSMs designed for the example memory controller, where each FSM is for stateF and stateS. 29
Figure 1.4. Schematics of the example memory controller. For simplicity, the data flow is abstracted out. 29
Figure 1.5. The combined FSM of the example memory controller. The red colored state (BF, BS) denotes a vulnerable state. 29
Figure 1.6. The workflow of RFuzz's mux coverage schemes for benign (left) and bug triggering inputs (right). 32
Figure 1.7. An overall framework of DifuzzRTL. It runs Both ISA and RTL simulations using the same... 35
Figure 1.8. Input generated by mutator. Each address is associated with an instruction and a list of interrupt events. 36
Figure 1.9. Algorithm of DifuzzRTL's control register identification 41
Figure 1.10. A register-coverage instrumentation of DifuzzRTL, which adds following three registers: regstate... 42
Figure 1.11. The workflow of DifuzzRTL's clock-sensitive register-coverage schemes for benign (left) and bug triggering inputs (right). 43
Figure 1.12. Average time(s) to find bug in synthetic RTL designs. 52
Figure 1.13. Reached states in synthtetic RTL designs. 52
Figure 1.14. Mux and register-coverage increments per fuzzing iterations. 56
Figure 1.15. Register-coverage increment in one iteration. 56
Figure 1.16. Mor1kx cappuccino 57
Figure 1.17. Rocket core 57
Figure 1.18. Boom core 57
Figure 1.19. Frequency of registers bit values in Rocket core when new coverage is explored. 58
Figure 1.20. Rocket 60
Figure 1.21. Boom 60
Figure 2.1. Pipeline stages 76
Figure 2.2. CPU micro-architecture. 76
Figure 2.3. General workflow of differential fuzz testing. 78
Figure 2.4. SpecDoctor fuzzer framework for finding transient execution vulnerabilities. 82
Figure 2.5. Example attack scenarios on RISC-V ISA. 83
Figure 2.6. Configured memory layout and hardware protection. 83
Figure 2.7. Simplified logic of DCache in RISC-V Boom CPU. tag array is indirectly wired into the valid signals. 89
Figure 2.8. High-level module containing four timing-change components. 90
Figure 2.9. Hash computation for summarizing the timing-change component's state. 90
Figure 2.10. Testcase with RoBLog from SpecDoctor phase 2 (left), and secret-transmit, hash-measure instructions generated from phase 3... 92
Figure 2.11. Mechanism of triggering Boombard bug. 103
Figure 2.12. Code snippet of Boombard. 103
Figure 2.13. Code snippet of Birgus. 108
Figure 3.1. Model fitting procedure and the customizable components 120
Figure 3.2. Problem situation of FairLearning 124
Figure 3.3. Algorithm for model fitting. 132
Figure 3.4. Blackbox of Baseline 135
Figure 3.5. Blackbox of FairFunction 135
Figure 3.6. Overall framework of FairLearning 140
Figure 3.7. Model fitting code example 143
Figure 3.8. Constructed AST 143
Figure 3.9. Example code for training ResNet18 model on Cifar10 dataset on FairLearning 147
Figure 3.10. Comparison of learning time for each task and model on Baseline, FL-unsafe, and FairLearning. Prepare denotes the time used for... 156
Figure 3.11. Overhead of FairLearning for data augmentation. 157
Figure 3.12. Overhead of FairLearning for parameter update. 157