Title Page
Abstract
Contents
Chapter 1. Introduction 17
1.1. Neuromorphic System 17
1.2. Synaptic Device for Neuromorphic System 21
1.3. Requirements of Neural Network Implementation 25
1.4. Outline of the Dissertation 30
Chapter 2. Overshoot Suppression Layer Inserted RRAM 32
2.1. Concept 32
2.2. Fabrication 40
2.3. Measurement Results 47
2.3.1. DC Characteristics 47
2.3.2. Multi-bit Characteristics 57
2.3.3. Reliability Characteristics 63
Chapter 3. Yield Enhancement of OSL RRAM 65
3.1. Fabrication Optimization 65
3.1.1. Mask Layout and Photo Lithography 65
3.1.2. TiOx Reactive Sputtering Conditions[이미지참조] 70
3.2. Aluminum Oxide Inserted OSL RRAM 76
3.2.1. Aluminum Oxide Formation 76
3.2.2. Comparison of TiOy and AlOy-based OSL devices[이미지참조] 84
3.2.3. Anneal Process Optimization 88
3.2.4. Multi-bit and Reliability Characteristics 95
Chapter 4. Array Operation and Neural Network Implementation 102
4.1. Measurement Condition Setup 102
4.1.1. Measurement Environment 102
4.1.2. Array Measurement 106
4.2. SNN Implementation 109
4.2.1. Network Configuration 109
4.2.2. Inference and Recognition Accuracy 112
4.3. Accurate Weight Transfer Scheme for SNN Implementation 125
4.3.1. Accurate Weight Transfer Scheme 125
4.3.2. Inference and Recognition Accuracy 130
Chapter 5. Conclusion 136
Bibliography 140
초록 147
List of Publications 151
Table 1.1. Candidates for the synaptic device. 23
Table 1.2. Comparison of previous studies implementing 0T-1R RRAM arrays and the study presented in this dissertation. 28
Table 2.1. Comparison of the conduction mechanism and switching characteristics of various types of RRAM. 34
Table 2.2. Calculated resistance by assuming resistivity from 10¯³ Ωm to 10¯⁵ Ωm and filament diameter from 1 nm to 25 nm. 38
Table 3.1. Total yield and failure mode based on device type and sputtering power. 75
Fig. 1.1. Data transfer bottleneck in a serially connected Von-Neumann architecture. 19
Fig. 1.2. (a) schematic diagram of the biological connection between a neuron and synapse and (b) an up-scale image of the synapse. 20
Fig. 1.3. Array and cell structure comparison of (a) 1T-1R structure and (b) 0T-1R 24
Fig. 1.4. Conventional filamentary metal-oxide RRAM resistive switching characteristics (a) without current compliance or (b) with current compliance. 27
Fig. 1.5. Method to achieve multi-bit characteristics of RRAM by (a) changing current compliance and (b) reset voltage. 29
Fig. 2.1. Structural diagram of conducting filament formation in OSL RRAM. 36
Fig. 2.2. (a) c-AFM measurement for determining conducting filament diameter, (b) enlarged contour map of Fig. 2.1 (a), and (c) current flowing at the cross-sectioned 37
Fig. 2.3. Resistivity comparison between resistor materials and titanium suboxide based on oxygen composition. 38
Fig. 2.4. (a) Expected OSL characteristics at the Al₂O₃/TiOx -based RRAM and (b) DC sweep characteristics of a Pt/TiOx/Ti/Pt device to evaluate OSL at oxygen...[이미지참조] 39
Fig. 2.5. Fabrication process flow of cross-point RRAM and schematic diagram of REF RRAM and OSL RRAM structure with each layer information. 42
Fig. 2.6. Process flow of cross-point array with OSL RRAM. 43
Fig. 2.7. SEM images of (a) fabricated single devices, (b) A 32 x 32 array, (c) A 16 x 16 array, (d) A 8 x 8 array, and (e) A cross-section of the cross-point region. 44
Fig. 2.8. (a) SEM and (b) TEM images of the switching layer of OSL. 45
Fig. 2.9. (a) XPS analysis on the TiOx and TiOy layers to verify their oxygen composition and binding energy of titanium and (b) oxygen.[이미지참조] 46
Fig. 2.10. DC sweep characteristics of REF and OSL1 devices until hard breakdown. 48
Fig. 2.11. Forming, set, and reset switching operations of (a) REF and (b) OSL1 devices. 49
Fig. 2.12. Soft breakdown characteristics of the OSL1 device according to the thickness of the switching layer (Al₂O₃) and OSL (TiOy).[이미지참조] 51
Fig. 2.13. (a) Voltage variation of OSL1 and (b) REF devices in set, reset 54
Fig. 2.14. (a) TEM image of optimized OSL1 device and (b) resistive switching characteristics for 50 devices. 55
Fig. 2.15. (a) DC sweep characteristics of OSL1 and optimized OSL1 devices until hard breakdown and (b) a magnified image of the overshoot suppression region. 56
Fig. 2.16. Comparison of forming voltage for devices without OSL, OSL1, and optimized OSL1. 57
Fig. 2.17. Gradual switching characteristics according to the ISPP pulse width of (a) 100 ns, (b) 1 µs, (c) 10 µs, and (d) 100 µs. 60
Fig. 2.18. (a) 4-bit multilevel characteristics of optimized OSL1 devices as measured with the ISPVA scheme. (b) The number of pulses needed to shift... 61
Fig. 2.19. Target weight tuning operation for 80 cells in a 16 x 16 array by using the ISPVA scheme from pristine states to target weight (a) 1µA and (b)... 62
Fig. 2.20. (a) Retention of 4-bit conductance states at room temperature. (b) Retention of four conductance states at 85℃. (c) Cumulative distribution of 4-... 64
Fig. 3.1. (a) Schematic diagrams of the method for lift-off processing using negative PR with an undercut and (b) positive double PR with a PR recess. 67
Fig. 3.2. (a) Schematic of the lift-off process using high-step coverage metal deposition and (b) FIB failure images after lift-off because of the metal fence at... 68
Fig. 3.3. (a) Mask layout with the development monitoring pattern, and (b) PR removal images at the development monitoring pattern according to the... 69
Fig. 3.4. Failure types of RRAM: (a) initial failure, (b) reset failure, and (c) HRS stuck. 73
Fig. 3.5. (a) tendency for the forming voltage to ascend as the sputtering power increases. (b) Good die yield for REF and OSL devices based on the sputtering power. 74
Fig. 3.6. Schematic, TEM, and EDS results of (a) an OSL2 device with Al insertion and (b) a REF device without an OSL. 78
Fig. 3.7. (a) TEM image of the OSL2 device with TE Al 100 nm. (b) EDS image of the OSL2 device with O, Al, and Ti atomic percentage. 81
Fig. 3.8. (a) Pristine DC sweep characteristics of the REF device until hardb reakdown depending on the oxygen composition in TiOx, and (b) resistive...[이미지참조] 82
Fig. 3.9. (a) Pristine DC sweep characteristics of the OSL2 device until hard breakdown depending on the oxygen composition in TiOx, and (b) resistive switching...[이미지참조] 83
Fig. 3.10. DC sweep characteristics of (a) OSL1 and (b) OSL2 with 20 devices. And D2D voltage variation at (c) set and (d) reset switching. DC sweep characteristics... 86
Fig. 3.11. Overshoot suppression characteristics depending on the annealing in (a) OSL1 and (b) OSL2 devices. 87
Fig. 3.12. (a) Schematic representation of Ti diffusion into the Al₂O₃ switching layer as a function of annealing temperature. (b) Pristine current variation with respect to... 90
Fig. 3.13. (a) XPS analysis results of Ti 2p³/² for oxygen compositions of 1.64 and (b) 1.38.[이미지참조] 91
Fig. 3.14. (a) Annealing-dependent switching voltage and variation characteristics for OSL2 devices, and (b) forming yield as a function of annealing temperature. DC sweep characteristics... 93
Fig. 3.15. (a) Mean value and (b) standard deviation for switching voltage according to the annealing temperature, and (c) result of dividing the mean value by the standard deviation. 94
Fig. 3.16. (a) DC endurance characteristics of OSL2 RRAM device and (b) sweep curve between 1st cycle to 1000th cycle. (c) Pulse endurance by using ISPVA...[이미지참조] 96
Fig. 3.17. Cycle-to-cycle variation characteristics of endurance data in Fig. 3.13 (c). The cumulative distribution shows the variation of the set, reset switching voltage over the... 97
Fig. 3.18. Gradual switching characteristics based on the pulse width of OSL2 RRAM. ISPP was employed for LRS and HRS tuning. This process was repeated ten times. ISPP... 98
Fig. 3.19. ISPVA-based approach for tuning the target weight. The interval of target weight is 1 μA, and the tolerance was set to ±0.2 μA. The absolute values of the Vmin, Vmax,...[이미지참조] 100
Fig. 3.20. (a) Multi-bit pulse endurance for 3-bit conductance. Every 50 cycles, the conductance state was changed. (b) Retention characteristics for multi-bit conductance at... 101
Fig. 4.1. (a) Single-array size dicing for the package process and then an image after die bonding and wire bonding. (b) Pristine read current map and SEM image of the ESD failed... 105
Fig. 4.2. Fabricated (a) 16 x 16 array and (b) 32 x 32 array. 107
Fig. 4.3. (a) Total yield of 32 x 32 array and cumulative distribution of 3-bit implementation. (b) Read current map at the LRS and (c) HRS. 108
Fig. 4.4. (a) Schematic diagram of the inference process through a 784 x 16 x 10 spiking neural network using the MNIST test dataset. (b) Schematic of an excitatory synapse array... 111
Fig. 4.5. (a) 3-bit target weight (IG) map of the second fully connected layer of the SNN for MNIST classification. (b) Result of transferring target weight to a 16 x 10 OSL2 array.... 113
Fig. 4.6. (a) IG+ weight transfer error (IG+ target - IG+ transferred) map after 1st and (b) 2nd weight transfer. (c) IG-weight transfer error (IG- target - IG- transferred) map after 1st and (d) 2nd...[이미지참조] 114
Fig. 4.7. (a) Comparison of ideal and measured VMM values for 50 timesteps and 200 test images output nodes from 0 to 9 and (b) cumulative distribution of VMM error. (c)... 116
Fig. 4.8. (a) Changes in weight states prior to and following inference for all IG₊. (b) Change in IG₊ weights during inference and (c) weight error map by the retention...[이미지참조] 117
Fig. 4.9. Difference in classification accuracy based on weight transfer tolerance. 118
Fig. 4.10. (a) Schematic of 16 x 16 array for SPICE simulation at bit-line read scheme and (b) word-line read scheme. (b) Measured values of RWL, RBL, and Rline.[이미지참조] 122
Fig. 4.11. (a) Comparison of at-bit-line read scheme voltage drop at the reading of individual cells versus a simultaneous reading of all cells, with increasing RWL, (b) RBL,...[이미지참조] 123
Fig. 4.12. (a) DC sweep curve for applying the switching characteristics at a SPICE simulation and (b) its fitting curve until 0.2 V at HRS. (c) Comparison of current sum...[이미지참조] 124
Fig. 4.13. DC sweep curves, which represent a range of resistive switching voltage for implementing multi-bit characteristics. 127
Fig. 4.14. (a) Random weight map to evaluate the transfer schemes. (b) First transfer map and (c) the last transfer map for the HRS-first transfer scheme. (d) First transfer map and... 128
Fig. 4.15. (a) Results at first, (b) second, (c) third transfer for the LRS-first transfer scheme, and at first, (e) second, (f) third weight transfer for the HRS-first transfer scheme. 129
Fig. 4.16. Average absolute weight error according to the transfer scheme and cycle. 130
Fig. 4.17. (a) DC sweep characteristics according to the sputtering pressure 7.5 mTorr, (b) 12.5 mTorr, and (c) 15 mTorr 133
Fig. 4.18. (a) Weight transfer result to the 32 x 32 array. (b) Target weights and (c) transferred weights to the 32 x 32 array. 134
Fig. 4.19. (a) Comparison of measured VMM and calculated VMM for 20 output nodes with 30 time-steps and (b) cumulative distribution of VMM error. (c) comparison of classification accuracy... 135