Title Page
Abstract
Contents
Chapter 1. Introduction 15
1.1. Motivation 15
1.2. Thesis Organization 17
Chapter 2. Background on High-Speed Receiver 19
2.1. Basic Concepts in Seral Interface 19
2.1.1. Serial Links 19
2.1.2. Multi-Level Pulse-Amplitude Modulation 22
2.2. Equalization 24
2.2.1. Overview 24
2.2.2. Continuous Time Linear Equalizer 28
2.2.3. Programmable Gain Amplifier 33
2.2.4. Decision Feedback Equalizer 36
2.2.5. Equalizer Adaptation 39
2.3. Clock and Data Recovery 43
2.3.1. Overview 43
2.3.2. PI-based CDR 45
2.3.3. Types of PAM-4 Phase Detectors 49
Chapter 3. PAM-2 Receiver with Stochastic CTLE Adaptation 56
3.1. Overview 56
3.2. Proposed CTLE Adaptation 58
3.2.1. Concept 58
3.2.2. Number of Samples 61
3.2.3. Weight Searching Algorithm 63
3.3. Circuit Implementation 70
3.4. Measurement Results 72
Chapter 4. PAM-4 Receiver with Dead-zone Free SS-MMSE PD for CIS Link 77
4.1. Overview 77
4.2. Analysis of Conventional Baud-rate PDs and Proposed Dead-zone Free PAM-4 PD 81
4.2.1. Comparison between MM PD and MMSE PD 81
4.2.2. Dead-zone Effect of Conventional Baud-rate PD with Adaptive DFE 87
4.2.3. Proposed Dead-zone Free PAM-4 Baud-rate PD 89
4.3. Circuit Implementation 95
4.3.1. Architecture of the Proposed PAM-4 RX 95
4.3.2. Fixed dtLev Calibration 101
4.3.3. Multiple Loop Stability 103
4.4. Measurement Results 105
Chapter 5. Conclusion 111
Bibliography 113
초록 119
Table 2.1. Characteristics of PAM-M signaling. 23
Table 2.2. Comparison between 1st and 2nd order PI-based CDR.[이미지참조] 47
Table 3.1. Golden weight table 67
Table 3.2. Performance Comparison 76
Table 4.1. Comparison between MM PD and MMSE PD assuming 2 error samplers per UI. 85
Table 4.2. Performance summary and comparison 110
Fig. 2.1. Trends of data rate of industrial I/O standards in [9]. 20
Fig. 2.2. Typical architecture of high-speed transceiver in [10]. 21
Fig. 2.3. Eye diagram comparison between PAM-2 and PAM-4 signaling. 22
Fig. 2.4. Conceptual diagram of single bit response. 24
Fig. 2.5. Conceptual diagram of sampled single bit response. 25
Fig. 2.6. Conceptual diagram of equalizers at the receiver side. 26
Fig. 2.7. Schematic diagram of the conventional active CTLE. 28
Fig. 2.8. Gain controllability of CTLE: (a) Controlling RS and (b) CS.[이미지참조] 30
Fig. 2.9. Gain curves of channel, CTLE, channel·CTLE. 31
Fig. 2.10. Gain curves and eye diagrams of various boosting conditions: under-boosted, optimum-boosted, and over-boosted. 32
Fig. 2.11. PAM-4 eye diagrams with various PGA gain conditions: Optimum, weak, and strong. 33
Fig. 2.12. Schematic diagram of the conventional active PGA. 34
Fig. 2.13. Gain curves of the PGA with adjustable degeneration resistance 35
Fig. 2.14. Schematic diagram of the PAM-4 1-tap DFE 36
Fig. 2.15. Concept of DFE with single-bit response. 38
Fig. 2.16. Concept of CTLE adaptation with spectrum balancing method in [7]. 41
Fig. 2.17. Concept of CTLE adaptation with eye-opening monitor in [3]. 42
Fig. 2.18. (a) Mesochronous clocking architecture and (b) Plesiochronous clocking architecture. 43
Fig. 2.19. Conceptual diagram of the PI-based CDR. 45
Fig. 2.20. z-domain system model of (a) 1st order and (b) 2nd order PI-based CDR.[이미지참조] 46
Fig. 2.21. Comparison between two types of PDs in terms of required samplers: (a) 2x oversampling PD and (b) baud-rate PD. 49
Fig. 2.22. Edge distributions for (a) PAM-2 and (b) PAM-4 signaling. 50
Fig. 2.23. Concept of the proposed PAM-4 PD in [5]. 51
Fig. 2.24. Concept of the baud-rate PD in [15]. 52
Fig. 2.25. Single-bit responses with corresponding PD gain curves for (a) symmetric impulse response without adaptive DFE and (b) asymmetric impulse response with adaptive DFE. 53
Fig. 2.26. Unequalized MM CDR with pulse response in [16]. 54
Fig. 2.27. Stochastic PAM-4 PD proposed in [17]. 55
Fig. 3.1. Proposed receiver with stochastic control engine. 58
Fig. 3.2. Concept of the conventional edge-based CTLE adaptation and proposed CTLE adaptation by detecting sequential edge and data patterns. 59
Fig. 3.3. ISI information obtained through correlation according to different sequential patterns. 61
Fig. 3.4. (a) Selected channel models and CTLE model, (b) collected eye diagrams and histograms for various CTLE codes with 15dB loss channel model. 63
Fig. 3.5. Weight conditions that SCGSOUT should satisfy for one channel (top) where M is the optimum CTLE code, and several examples of the SCGS gain curves that applies the... 64
Fig. 3.6. (a) How the state Count Num is performed, and (b) weight searching algorithm that finds the golden weight set based-on epsilon constraint optimization. 65
Fig. 3.7. Final stochastic CTLE adaptation gain curve with the golden weight set for the selected channel models. 68
Fig. 3.8. Circuit implementation of the proposed receiver with referenceless CDR and stochastic CTLE adaptation. 70
Fig. 3.9. Microphotograph of the prototype and power breakdown. 72
Fig. 3.10. Measured channel insertion loss. 73
Fig. 3.11. Measured BER with sinusoidal jitter of 0.2 UIpp at 100 MHz by manually controlled CTLE code.[이미지참조] 74
Fig. 3.12. Measured JTOL of channel 3 with both referenceless CDR and CTLE adaptation is on. 75
Fig. 4.1. Conceptual diagram of the proposed PAM-4 adaptive receiver with dead-zone free baud-rate CDR and adaptive control engine. 79
Fig. 4.2. Detected transitions of (a) MM PD and (b) MMSE PD which assumes 2 error samplers per sampling phase. 84
Fig. 4.3. Single bit response and corresponding timing function of (a) conventional baud-rate PD without DFE, (b) conventional baud-rate PD with DFE. 87
Fig. 4.4. Working principle of the proposed SS-MMSE PD and the biased state. 89
Fig. 4.5. Proposed DF SS-MMSE PD: summation of SS-MMSE PD and weighted biased state. 91
Fig. 4.6. Conceptual diagram of the maximum VEO achievement. 92
Fig. 4.7. Simulation results of optimum beta for different insertion losses 93
Fig. 4.8. Overall block diagram of the proposed PAM-4 adaptive RX. 95
Fig. 4.9. (a) Schematic diagram of the ATT and (b) AC gain curves of ATT. 97
Fig. 4.10. (a) Schematic diagram of the PGA and (b) AC gain curves of PGA. 98
Fig. 4.11. (a) Schematic diagram of the CTLE and (b) AC gain curves of CTLE. 99
Fig. 4.12. Circuit Implementation of DF SS-MMSE CDR. 100
Fig. 4.13. Fixed dtLev calibration for non-linearity and offset of samplers. 101
Fig. 4.14. Schematic diagram of skew calibration. 102
Fig. 4.15. Simulation result of the simultaneous adaptation at data rate of 12 Gb/s. 103
Fig. 4.16. Block diagram of the measurement setup. 105
Fig. 4.17. (a) Chip photomicrograph and (b) measured power breakdown and (c) differential insertion loss. 106
Fig. 4.18. Measured recovered eye diagram with on-chip eye monitor. 107
Fig. 4.19. Measured (a) bathtub curve and (b) jitter tolerance curve. 109