Title Page
Abstract
Contents
Chapter 1. Introduction 16
1.1. Motivation 16
1.2. Thesis Organization 20
Chapter 2. Backgrounds 22
2.1. Overview 22
2.2. Internal Display Interface 31
2.2.1. Overview 31
2.2.2. AP-to-TED interface 36
Chapter 3. Design of High-Speed and Low-Power Transceiver 38
3.1. The Design of Transmitter 38
3.1.1. Proposed Pseudo Serializer 38
3.1.2. Proposed ISI-Mitigating MUX 42
3.1.3. Overall Sturucture of Transmitter 45
3.2. The Design of Receiver 47
3.2.1. Overview 47
3.2.1. Proposed Referenceless Hybrid Loop CDR 48
3.2.2. Overall Structure of Receiver 52
3.3.3. Circuit Implementation 54
3.4. Measurement Results 57
Chapter 4. Receiver with Fast Frequency Acquisition in Active mode and Fast Recovery from Sleep mode under Voltage Drift 64
4.1. Overview 64
4.2. Proposed Frequency Detector 67
4.2.1. PriorWork 67
4.2.2. Fast Frequency acquisition Using Linearity Fucntion 70
4.3. Proposed Hybrid CDR with Fast Recoveryfrom Sleep Mode under Voltage Drift 77
4.3.1. Hybrid Loop CDR with SVDC 77
4.4. Analog Front-End Supporting Sleep Mode 85
4.5. Circuit Implementation 89
4.5.1. Overall Structure 89
4.5.2. Command Controller 93
4.6. Measurement 94
4.6.1. Fast frequency tracking 98
4.6.2. Frequency recovery from sleep mode under supply voltage drift 104
Chapter 5. Conclusions 108
Bibliography 110
초록 120
Table 3.1. Comparision of the proposed transceiver with prior design 63
Table 4.1. Comparison table with other receivers supporting the sleep mode 107
Fig. 1.1. The display resolution changes of the Galaxy-S series 17
Fig. 1.2. Overall architecture of mobile application 19
Fig. 2.1. Depiction of parallel communication and series communication 23
Fig. 2.2. Simplified block diagram of serial link 23
Fig. 2.3. Block diagram of synchronous clocking architecture - forwarded clocking 25
Fig. 2.4. Block diagram of mesochronous clocking architecture - forwarded clocking 25
Fig. 2.5. Block diagram of mesochronous clocking architecture - common reference clock 27
Fig. 2.6. Block diagram of plesiochronous clocking archictecture 27
Fig. 2.7. Timing diagram of clocking scheme: (a) full-rate (b) half-rate (c) quarter-rate 30
Fig. 2.8. Description and specification of LVDS (low voltage differential signaling) 32
Fig. 2.9. Simplified block diagram of internal DisplayPort (iDP) PHY Electrical Sub-Layer 32
Fig. 2.10. MIPI Multimedia specification 34
Fig. 2.11. A conceptual view and description of the layers of DSI 34
Fig. 2.12. The per-pin data rate versus version for D-PHY 35
Fig. 2.13. Overall architecture of AP-to-TED interface 36
Fig. 2.14. Example illstration of Flexible Printed Circuit Board 37
Fig. 3.1. Overall sturcture of 2:1 serializer 39
Fig. 3.2. Overall structure of proposed pseudo serializer 41
Fig. 3.3. Structure of 2-to-1 MUX and timing diagram 41
Fig. 3.4. The schematic of conventional MUX 42
Fig. 3.5. Proposed ISI-mitigating MUX 43
Fig. 3.6. Timing diagram of ISI-Mitigating MUX 43
Fig. 3.7. Simulation results of (a) conventional MUX (b) ISI-Mitigating MUX 44
Fig. 3.8. Overall sturcture of proposed transmitter 46
Fig. 3.9. Proposed hybrid oscillator whose frequency is controlled by 4 different types of tail currents 49
Fig. 3.10. Frequency locking procedure of the proposed CDR: (a) digital loop activation, and (b) analog loop activation 50
Fig. 3.11. Simulation result of frequency locking procedure 51
Fig. 3.12. The overall structure of proposed receiver 53
Fig. 3.13. The circuit description of CTLE 54
Fig. 3.14. Frequency response of CTLE [post-simulation results] 55
Fig. 3.15. The components of a digital loop filter 56
Fig. 3.16. Die microphotograph 57
Fig. 3.17. Power breakdown of transceiver 58
Fig. 3.18. Measurement setup of proposed transceiver 58
Fig. 3.19. Measured eye diagram of transmitter output 59
Fig. 3.20. Measured jitter tolerance curve (BER〈10⁻¹²) 61
Fig. 3.21. Measured BER bathtub curve 61
Fig. 3.22. Measured frequency acquisition behavior 62
Fig. 3.23. Measured 5-GHz recovered clock 62
Fig. 4.1. Concetual diagram of proposed receiver 66
Fig. 4.2. Concept of stochastic FPD 68
Fig. 4.3. Flow chart of design techniques of stochastic frequency-phase detector 68
Fig. 4.4. Achieved (a) phase detection gain curve (b) frequency detection gain curve 69
Fig. 4.5. The main stages of FSM 70
Fig. 4.6. Simulated frequency detection gain curve by varing the averaging time 72
Fig. 4.7. The concept of the frequeny tracking in the FD gain curve 72
Fig. 4.8. Simulation results of error accumulation and calculation 74
Fig. 4.9. The simulation result of frequency transient behavior 75
Fig. 4.10. The simulation results of the locking time between the conventonal frequency tracking and proposed frequency tracking 76
Fig. 4.11. Simulated oscillator frequency sensitivity to ACTRL for various supply voltages (a) without SVDC, (b) with SVDC 79
Fig. 4.12. Simulated current changes versus a change in VDDOSC[이미지참조] 80
Fig. 4.13. Hybrid oscillator with SVDC 80
Fig. 4.14. Circuit implementation of supply voltage drift cancellation 82
Fig. 4.15. The simulation results of (a) bias voltage change in a BVG (b) current of frequency tuning cell change versus a change in VDDOSC 82
Fig. 4.16. The simulation results of current change versus a change in VDDOSC for temperature 84
Fig. 4.17. The simulation results of current change versus a change in VDDOSC for corner variation 84
Fig. 4.18. Current switch on a) current bias of CTLE b) tail current of hybrid oscillator 85
Fig. 4.19. Simulation result for current variation on acive mode, sleep mode, wake-up 87
Fig. 4.20. Simulation results for the process of storing and restoring code. 88
Fig. 4.21. Overall structure of the proposed receiver 90
Fig. 4.22. Circuit description of the HOSC with SVDC including the simulation results of SVDC 92
Fig. 4.23. The simulation results of behavior modeling of command controller 93
Fig. 4.24. Die microphotograph 94
Fig. 4.25. Meausrement setup for (a) receiver performance (b) SVDC 95
Fig. 4.26. Detailed measurement setup for verifying receiver's performance 95
Fig. 4.27. Power breakdown of active mode and sleep mode 97
Fig. 4.28. Measured jitter tolerance curve 97
Fig. 4.29. Measured frequency acquisition behaviors before post-processing @ 10 Gb/s PRBS-7 with varying inital HOSC frequency (a) 4.55 GHz, (b) 4.37 GHz, (c) 4.87 GHz 99
Fig. 4.30. Measured frequency acquisition behaviors with varying intial DCO frequency (a) 4.55~5.83 GHz, (b) 4.37~5.65 GHz, (c) 4.87~6.15 GHz 101
Fig. 4.31. Measured frequency acquisition behaviors with varying averaging time (a) 1000 UI, (b) 2520 UI 103
Fig. 4.32. Measured frequency of free-running HOSC 104
Fig. 4.33. Post-processed waveform of frequency recovery after sleep mode. (a) Initial active mode voltage : 1 V and (b) 0.95 V, 1.05 V 105