Title Page
Abstract
Contents
Chapter 1. Introduction 23
1.1. Battery Configuration in EV and BESS 24
1.2. Cell-Inconsistency and its Impact on the Performance of the Cells 29
1.2.1. Cell-Inconsistency in Series Connection 29
1.2.2. Cell-Inconsistency in Parallel Connection 31
1.2.3. Hardware Test Datasets for Cell-inconsistency 33
1.3. Overview of Battery Management System in EV and BESS 38
1.4. Battery Equalizer 39
1.4.1. Dissipative Energy Schemes 40
1.4.2. Regenerative Energy Schemes I - Converter Type 42
1.4.3. Regenerative Energy Schemes II - SET-E Types 43
1.5. Battery State Estimation and Monitoring 46
1.6. Performance Indices for Battery Equalizer 48
1.7. Level of Equalization for the Battery System 54
1.8. Problem Identification 57
1.9. Objectives and Contributions of the Thesis 58
1.10. Outlines of the Thesis 59
Chapter 2. Switch-Matrix Capacitor Equalizer for Cell Equalization 61
2.1. Proposed Switch-Matrix Capacitor Equalizer 61
2.1.1. Topological Configuration and Equalization Principle 62
2.1.2. Optimal Pairing Algorithm for Equalization Strategy 66
2.2. Optimal Design Consideration for the SMC-E 69
2.2.1. Switching Frequency and Equalization Capacitance 69
2.2.2. Balancing Capacitance and Capacitor Size 72
2.3. Experimental Verification 82
2.3.1. Design Verification 83
2.3.2. Performance Assessment 85
2.4. Conclusion of the Chapter 89
Chapter 3. Novel Simulation Techniques for the Performance Assessment of SET-E in Long-term Operation 90
3.1. Real Time Simulation System 91
3.1.1. RTSS Platform 91
3.1.2. Performance Verification 94
3.2. Unified Average Model based Simulation 100
3.2.1. UA-model: Operating Principle 100
3.2.2. Performance Comparison by UA-model 106
3.2.3. Design Assessment by UA-model 114
Chapter 4. Switch-Matrix Capacitor Equalizer for Module Equalization 116
4.1. Extension of the SMC-E for Series-connected Modules 117
4.1.1. Use Cases and Conventional Structure 117
4.1.2. Equalization Speed vs. Number of Cells 119
4.1.3. Module Equalization Strategy for the Series-connected Modules 124
4.1.4. Hybrid Control Algorithm Between the Cell and Module Equalization 128
4.1.5. Design Consideration 133
4.1.6. Performance Verification 134
4.2. Extension of SMC-E for Parallel-connected Modules 145
4.2.1. Conventional Structure 145
4.2.2. Proposed Equalization Strategy for Parallel-connected Battery Modules 146
4.2.3. Performance Verification 154
4.3. Conclusion of the Chapter 163
Chapter 5. Conclusion and Future Works 164
5.1. Conclusions 164
5.2. Future Works 165
Biography 167
References 172
Table 1.1. COMPARISON OF BMIC FEATURES. 39
Table 1.2. CLASSIFICATION OF BATTERY EQUALIZERS 40
Table 2.1. BALANCING-CURRENT MATRIX 66
Table 2.2. DESIGN PARAMETER SUMMARY 69
Table 2.3. CAPACITOR SIZING-OPTION COMPARISON 74
Table 2.4. SWITCH-MATRIX STRUCTURE COMPARISON 78
Table 2.5. TRUTH TABLE OF SIGNAL EXTENSION FOR 4S1P BATTERY STRING 79
Table 2.6. EXPERIMENTAL RESULTS-BATTERY VOLTAGES 88
Table 3.1. EXPERIMENTAL RESULTS vs. HIL RESULTS-BATTERY VOLTAGES 94
Table 3.2. SUMMARY OF PERFORMANCE INDICES 97
Table 3.3. AVERAGE EQUALIZING CURRENT CALCULATION FOR UA-MODEL 105
Table 3.4. CIRCUIT PARAMETER SETTING 107
Table 4.1. TRANSFERRED CHARGE OF THE CELLS AFTER THE EQUALIZATION PROCESS 121
Table 4.2. TEST SETUP ON RTSS FOR SERIES MODULAR EQUALIZATION 135
Table 4.3. TEST SETUP ON RTSS FOR PARALLEL CONNECTED MODULES 155
Fig. 1.1. Battery configuration in ESS: (a) nSmP configuration; (b) nPmS configuration. problem of the conventional equalizers are identified, which highlights the research motivation... 24
Fig. 1.2. Example of cell configuration in EV: (a) Pouch type; (b) Cylindrical type. 25
Fig. 1.3. Battery configuration in telecommunication and datacenter applications. 26
Fig. 1.4. Life cycle and seconds-life battery concept. 27
Fig. 1.5. Cell-inconsistency in series connection: (a) Mechanism of the over-charging and under-charging issue; (b) Thermal runaway effect of the cells. 29
Fig. 1.6. Cell-inconsistency in parallel connection: (a) Equivalent circuit of parallel connected battery module; (b) Equivalent circuit of hot-swap operation. 31
Fig. 1.7. Experimental setup for the aging assessment. 34
Fig. 1.8. Aging pattern and its probability: (a) Capacity vs. number of cycles; (b) SOH distribution of 34 retired battery modules in EV. 35
Fig. 1.9. Distribution illustration for 50,000 Li-ion 18650 cells (3.7V-3Ah-20 mΩ): (a) Available Capacity; (b) DC resistance. 36
Fig. 1.10. Impact of the cell-inconsistency: (a) un-equal current sharing of the branches; (b) SOC mismatching during the operation. 37
Fig. 1.11. Modular structure of the BMS in EV and BESS. 38
Fig. 1.12. Dissipative energy scheme: (a) switched-resistor; (b) variable resistance using MOSFET. 40
Fig. 1.13. Regenerative energy scheme group - Converter & Transformer type: (a) Individual converter; (b) Switch-matrix converter. 41
Fig. 1.14. Regenerative energy scheme group - Transformer type: (a) Individual transformer; (b) multi-winding transformer. 43
Fig. 1.15. Energy regenerative schemes II - SET-E types: (a) SI-E, (b) SC-E, (c) SR-E. 44
Fig. 1.16. Energy density comparison of inductor vs. capacitor. 45
Fig. 1.17. Various performance indices for the equalizer. 49
Fig. 1.18. Slew rate of SOC and Voltage equalization: (a) SOC profiles of two equalizers with their slew rate profile; (b) Voltage profiles of two equalizers with their slew rate profile. 50
Fig. 1.19. Total changed charge concept: (a) charge transferring during the equalizing operation; (b) Total changed charge of the cells. 52
Fig. 1.20. SOC distribution of the cells in various scenarios: (a) Four cells in descending order; (b) Four cells in convex order; (c) Four cells in concave order; (d) Eight cells in descending order. 53
Fig. 1.21. Inconsistency between the cells and groups due to the packing process. 54
Fig. 1.22. Polarization effect of the battery during the discharging operation. 55
Fig. 1.23. Inconsistency and equalization level classification: (a) Level I: Cell-to-cell equalization; (b) Level II: Module-to-module equalization; (c) Level III: all cells in every module equalization. 56
Fig. 1.24. Remaining problem of conventional structure of BMS: (a) impact of energy distribution to the equalization; (b) complete block diagram of a BMS 57
Fig. 2.1. Proposed Switch-Matrix Capacitor Equalizer: (a) Topology configuration ; (b) Operation principle of one equalization cycle. 63
Fig. 2.2. Equivalent circuit of the SMC-E during the equalization 64
Fig. 2.3. Theoretical waveform of the SMC-E. 65
Fig. 2.4. Optimal pairing algorithm: (a) Control flowchart; (b) Timing diagram of the current scanning process. 66
Fig. 2.5. Average balancing current and power loss of the SMC-E for two cells: (a) △V=300mV; (b) △V=200mV; (c) △V=100mV. 69
Fig. 2.6. Capacitor type comparison. 73
Fig. 2.7. Practical routing layout of parallel capacitors: (a) first-in/first-out; (b) first-in/last-out. 75
Fig. 2.8. Switch-matrix configuration: (a) Multiplexer structure; (b) Odd-Even structure. 77
Fig. 2.9. Switch configuration and gating circuit 78
Fig. 2.10. PWM signal extension for SMC-E. 79
Fig. 2.11. Sampling diagram and current sensing circuit: (a) Sampling diagram; (b) shunt-resistor-based measuring method; (c) Hall-sensor-based measuring method. 81
Fig. 2.12. Operation waveform of the SMC-E: (a) Design #1-1000µF/10kHz; (b) Design #1-4000µF/20kHz. 82
Fig. 2.13. Capacitor Current and Voltage waveform of SMC-E with Li-po pouch cell: (a) △V=100mV; (b) (a) △V=250mV. 84
Fig. 2.14. Equalization current of SMC-E at various voltage deviation levels. 84
Fig. 2.15. Experimental Setup of SMC-E for four 18650 cells (3.6V-2.6Ah). 85
Fig. 2.16. Current and voltage waveform of the capacitor: (a) one equalization cycle-Timebase 640ms/div; (b) scanning waveform of two cell-pairings-Timebase 20µs. 86
Fig. 2.17. Voltage profile of the cells in: (a) Case 1; (b) Case 2; (c) Case 3. 87
Fig. 3.1. Voltage and current of the SC-E during: Original capacity setting; (b) 10 times scaled-down of capacity. 92
Fig. 3.2. RTSS platform setting: (a) Circuit model on RTSS; (b) SCADA platform for result monitoring. 93
Fig. 3.3. Voltage profile comparison: (a) the experimental results; (b) HIL test for 4 cells. 95
Fig. 3.4. Initial energy distribution: (a) Scenario #1: Descending order; (b) Scenario #2: Convex order; (c) Scenario #3: Concave order. 96
Fig. 3.5. SOC and Voltage profiles of the cells in: (a) Scenario #1; (b) Scenario #2; (c) Scenario #3. 97
Fig. 3.6. Cycling sequence for 4S1P cell string. 98
Fig. 3.7. Operation profiles of the cells during cycling process: (a) voltage profiles, (b) SOC profiles, (c) current profiles. 99
Fig. 3.8. Operating principle of various equalizers: (a) SC-E, (b) SR-E, (c) SI-E, (d) SMC-E. 101
Fig. 3.9. Average model evolution of SET-Es: (a) Equivalent circuit based on the operation principle, (b) Conventional equivalent resistance model, (c) UA-model. 102
Fig. 3.10. Implementation of UA-model: (a) autonomous SET-E type; (b) governed switch-matrix type (SMC-E). 106
Fig. 3.11. Voltage profiles of the cells during the equalization by RTSS, REQ model, and UA-model: (a) SI-E; (b) SC-E; (c) SR-E; and (d) SMC-E.[이미지참조] 108
Fig. 3.12. SOC profiles of the cells during the equalization by RTSS, REQ model, and UA-model: (a) SI-E; (b) SC-E; (c) SR-E; and (d) SMC-E.[이미지참조] 108
Fig. 3.13. Current profiles of the cells during the equalization by RTSS, REQ model, and UA-model: (a) SI-E; (b) SC-E; (c) SR-E; and (d) SMC-E.[이미지참조] 109
Fig. 3.14. SOC distribution of the cells in various scenarios: (a) Four cells descending; (b) Four cells convex; (c) Four cells concave; (d) Eight cells descending. 110
Fig. 3.15. Voltage profiles of the cells during the equalization by RTSS, REQ model, and UA-model: (a) SI-E; (b) SC-E; (c) SR-E; and (d) SMC-E.[이미지참조] 110
Fig. 3.16. SOC profiles of the cells by UA-model: (a) SI-E; (b) SC-E; (c) SR-E; and (d) SMC-E. 111
Fig. 3.17. Performance stability under various test scenarios of: (a) SI-E ; (b) SC-E; (c) SR-E; (d) SMC-E. 113
Fig. 3.18. UA-model based performance comparison of various design combination: (a) Voltage profiles; (b) SOC profiles; (b) Current profiles. 114
Fig. 4.1. Modular structure of the SMC-E for: (a) Series-connected battery modules; (b) Parallel-connected battery modules. 117
Fig. 4.2. Modular equalization in: (a) Battery energy storage system; (b) Maintenance in car repairing shop. 118
Fig. 4.3. Conventional equalizer structure for the multiple battery modules. 119
Fig. 4.4. Influence of cell number to the equalization: (a) in 8S1P battery string; (b) in 12S1P battery string. 120
Fig. 4.5. SOC profiles of the cells during the equalization of: (a) Passive balancing method; (b) SMC-E under Scenario #1; (c) SMC-E under scenario #2; (d) SMC-E under scenario... 122
Fig. 4.6. Proposed modular equalization strategy for series-connected battery modules: (a) topology configuration; (b) Phase MA; (c) Phase MB. 124
Fig. 4.7. Operating principle of the module balancing: (a) Equivalent circuit of two modules; (b) Phase MA; (c) Phase MB. 125
Fig. 4.8. Average current and power loss of the equalizer: (a) △V=1.2V; (b) △V=0.8V; (c) △V=0.4V. 127
Fig. 4.9. Control flowchart for the equalization of both cell and module levels: (a) Hybrid governed-autonomously strategy; (b) Full autonomously strategy. 129
Fig. 4.10. Switching pattern of the autonomous control strategy: (a) cell-to-cell; (b) Sub-module to sub-module; (c) Module-to-module. 131
Fig. 4.11. Divide strategy in different number of cells: (a) Even dividing; (b) Odd dividing. 132
Fig. 4.12. Graphic illustration of the equalization by the autonomous control strategy: (a) cell-to-cell; (b) Sub-module to sub-module; (c) Module-to-module. 133
Fig. 4.13. Schematic of the gating for the modular SMC-E unit. 134
Fig. 4.14. Operating profiles of single SMC-E for 8S1P string: (a) Voltage profiles of the cells insides the modules; (b) SOC profiles of the cells. 135
Fig. 4.15. Operation profile of the governed strategy: (a) voltage profile of the cells insides the modules; (b) voltage profile of two modules; (c) SOC profile of the cells insides the modules;... 136
Fig. 4.16. Initial SOC distribution of the cells (Module #1-C#1, C#2, C#3, C#4; Module #2-C#5, C#6, C#7, C#8): (a) Descending distribution; (b) Convex distribution; (c)... 138
Fig. 4.17. Voltage profile of the cells during the autonomous equalization under three test scenarios: (a) Inside module #1; (b) Inside module #2. 139
Fig. 4.18. SOC profile of the cells during the autonomous equalization under three test scenarios: (a) Inside module #1; (b) Inside module #2. 140
Fig. 4.19. Operation profiles during the autonomous equalization under three test scenarios: (a) Voltage profile of all cells; (b) SOC profile of all cells; (b) SOC profile of all cells; (c)... 141
Fig. 4.20. Current profiles of one equalization cycle by autonomous strategy 141
Fig. 4.21. Experimental setup of the SMC-E for modular equalizing strategy 142
Fig. 4.22. Hardware design of the SMC-E in every experiments 142
Fig. 4.23. Operating waveform of the SMC-E: (a) Cell equalization at △V=250 mV; (b) Cell equalization at △V=100 mV; (c) Sub-modules equalization; (a) Module equalization. 143
Fig. 4.24. Voltage profile during the equalizing process: (a) versus cell voltages inside module #1; (b) versus cell voltages inside module #2; (c) versus all cells; (d) module #1 versus... 144
Fig. 4.25. Conventional equalization circuits of the parallel connected battery modules: (a) Relay-based scheduling method; (b) dynamic resistance equalization. 145
Fig. 4.26. Self balancing effect in the parallel connected battery module when they are connected together at t=0 146
Fig. 4.27. Modular strategy for parallel connected battery module: (a) Topology configuration; (b) Operation principle - Phase A; (c) Operation principle - Phase B. 147
Fig. 4.28. Operation of the parallel-connected battery modules: (a) Parallel modules in discharge process; (b) Equivalent circuit of the switched capacitor equalizer. 148
Fig. 4.29. Module equalization strategy in non-IDLE modes: (a) Req vs. fs and D; (b) Equivalent circuit using Req model.[이미지참조] 152
Fig. 4.30. Average current and power loss of the equalizer: (a) △V=1.2V; (b) △V=0.8V; (c) △V=0.4V. 154
Fig. 4.31. Operation profiles of the battery modules during IDLE mode: (a) Voltage profile; (b) SOC profile; (c) Current profile. 156
Fig. 4.32. Operation profiles of the battery modules during Discharging process under Combined strategy and non-IDLE only strategy: (a) Voltage profile; (b) SOC profile; 157
Fig. 4.33. Current profiles of the battery modules during the Discharging process under: (a) Combined strategy; (b) non-IDLE-only strategy. 160
Fig. 4.34. Current waveform of the battery modules during: (a) Pre-equalization; (b) unequal discharging/charging process. 161
Fig. 4.35. Operating profiles of the battery modules during Charging process: (a) Voltage profile; (b) SOC profile; (c) Current profile. 162