Title Page
ABSTRACT
국문 초록
PREFACE
Contents
NOMENCLATURE (or LIST OF SYMBOLS) 23
CHAPTER 1. INTRODUCTION 26
CHAPTER 2. D-band low power sub-harmonic receiver 27
2.1. Motivation 27
2.2. Design of the D-band circuit blocks 28
2.2.1. Design of the D-band low noise amplifier 28
2.2.2. Design of the D-band sub-harmonic mixer 35
2.2.3. Design of the frequency doubler 41
2.3. Integrated D-band sub-harmonic receiver 47
CHAPTER 3. Q-band image rejection receiver 54
3.1. Motivation 54
3.2. Design of the Q-band circuit blocks 54
3.2.1. Design of the Q-band low noise amplifier 54
3.2.2. Design of the Q-band down conversion mixer 57
3.2.3. Design of the Q-band voltage-controlled oscillator 61
3.2.3. Design of the frequency divider chain 63
3.3. Integrated Q-band image-rejection receiver 74
CHAPTER 4. Ku-band GaAs multifunction transmitter and receiver 78
4.1. Motivation 78
4.2. Design of the GaAs circuit blocks 79
4.2.1. Design of the GaAs low noise amplifier 79
4.2.2. Design of the GaAs medium power amplifier 82
4.2.3. Design of the GaAs 5-bit digital attenuator 83
4.2.4. Design of the GaAs 4-bit digital phase shifter 89
4.2.5. Design of the serial-to-parallel converter (SPC) 92
4.2.5. Design of the distributed drain mixer 95
4.3. Integrated GaAs multifunction transmitter and receiver 107
CHAPTER 5. CONCLUSION 116
REFERENCES(or BIBLIOGRAPHY) 118
Table 1. Performance comparison to other published D-band CMOS receiver 53
Table 2. Performance comparison to other silicon-based image-rejection receiver 77
Table 3. Design parameters of the GaAs 5-bit digital attenuator 86
Table 4. Performance comparison to other published GaAs distributed mixer 106
Table 5. Performance comparison to other published GaAs multifunction chips 115
Figure 1. Schematic diagram of the D-band low noise amplifier 29
Figure 2. Simplified schematic of the differential transistor pair with neutralization capacitor 29
Figure 3. Simulated Gmax, NFmin and dc consumption of the neutralized differential transistor pair versus transistor size at 136 GHz[이미지참조] 30
Figure 4. Simplified layout of differential transistor pair 30
Figure 5. Simulated amplitude and phase imbalance of the differential pair with transformer versus RF frequency 32
Figure 6. Simulated total gain and amplitude mismatch versus RF frequency with arranged inverted alternately or not 33
Figure 7. Chip micrograph of the D-band LNA 34
Figure 8. Measured s-parameters of the D-band LNA 34
Figure 9. Schematic diagram of the sub-harmonic mixer 35
Figure 10. Characteristic of drain-source current (iDS) versus gate-source voltage (vGS) in the MOS transistor.[이미지참조] 36
Figure 11. Simulated Gm2 and normalized conversion gain of the SHM core according to VLO[이미지참조] 38
Figure 12. Simulated performance of the SHM core: (a) conversion gain versus RF frequency with fLO=70 GHz, and (b) LO isolation versus LO frequency[이미지참조] 40
Figure 13. Simulated conversion gain at each output node of the IF amplifier and return loss of the buffer stage versus IF frequency 41
Figure 14. Schematic diagram of the frequency doubler 42
Figure 15. Simulated conversion gain of the frequency doubler versus input frequency with Pin=0 dBm[이미지참조] 42
Figure 16. Chip micrograph of the D-band SHM integrated with frequency doubler and IF amplifier 43
Figure 17. Measured conversion gain of the D-band SHM integrated with frequency doubler and IF amplifier: (a) conversion gain versus PLO with fIF=0.5 GHz and fRF=136.5...[이미지참조] 46
Figure 18. Measured IF output power and conversion gain versus RF input power of the SHM integrated with frequency doubler and IF amplifier. fIF=0.5 GHz, fRF=136.5...[이미지참조] 46
Figure 19. Measured LO-to-RF and 2*LO-to-RF isolation of the SHM integrated with frequency doubler and IF amplifier. PLO=0 dBm[이미지참조] 47
Figure 20. (a) Block diagram and (b) chip micrograph of the integrated D-band sub-harmonic receiver 48
Figure 21. Measurement setup of the integrated D-band sub-harmonic receiver 49
Figure 22. Measured conversion gain of the sub-harmonic receiver: (a) conversion gain and NF with fixed LO frequency (fLO=34.0 GHz and PLO=0 dBm), (b) conversion gain...[이미지참조] 50
Figure 23. Measured IF output power and conversion gain versus RF input power of the sub-harmonic receiver with fIF=1.0 GHz, fRF=137.0 GHz, and PLO=0 dBm[이미지참조] 51
Figure 24. Measured EVM with 16/64-QAM modulated waveforms 52
Figure 25. (a) Schematic diagram and (b) chip micrograph of the Q-band low noise amplifier 56
Figure 26. Measurement results of the Q-band LNA. (a) s-parameters and noise figure performance, (b) output power and power gain versus input power at 33.5GHz 57
Figure 27. Schematic diagram of the Q-band down conversion mixer 58
Figure 28. Chip micrograph of the Q-band down conversion mixer 59
Figure 29. Measured conversion gain of the Q-band down conversion mixer: (a) conversion gain versus RF frequency with fLO=40 GHz and PLO=0 dBm, (b) conversion...[이미지참조] 60
Figure 30. Schematic diagram of the Q-band voltage-controlled oscillator 61
Figure 31. Chip micrograph of the Q-band voltage-controlled oscillator 62
Figure 32. Measured oscillation frequency and output power of the Q-band VCO versus the varactor control voltage 62
Figure 33. Schematic diagram of the conventional ILFD with the source follower buffer 63
Figure 34. Schematic diagram of the inductive peaking ILFD with the source follower buffer 64
Figure 35. Schematic diagram of the ILFD using the varactors with the source follower buffer 65
Figure 36. Chip micrograph of (a) the conventional ILFD, (b) the inductive peaking ILFD, and (c) the ILFD with the varactors 67
Figure 37. Measurement results of the conventional ILFD: (a) spectrum of free-running state and injection-locked state. (b) input sensitivity curve. 68
Figure 38. Measured input sensitivity curves of (a) the inductive peaking ILFD, and (b) the ILFD with the varactors. 70
Figure 39. LR and output power of three ILFDs with Pinj=0 dBm[이미지참조] 70
Figure 40. Schematic diagram of the CML divider 71
Figure 41. (a) Schematic diagram, and (b) chip micrograph of the VCO with 1/16 divider chain test-cut. 72
Figure 42. Measurement results of the VCO with 1/16 divider test-cut: (a) phase noise at 10-MHz offset, and (b) Output frequency of the VCO and divider versus control voltage... 73
Figure 43. (a) Block diagram and (b) chip micrograph of the integrated Q-band image-rejection receiver 75
Figure 44. Performance of the Q-band image-rejection receiver: (a) conversion gain, IMRR and NF versus IF frequency (b) IF output power and conversion gain versus RF... 76
Figure 45. Schematic diagram and chip micrograph of the GaAs LNA 79
Figure 46. Simulated MAG and NFmin of the 2 x 50-μm transistor with various values of Ls[이미지참조] 80
Figure 47. Measurement results of the GaAs LNA. (a) Gain and noise figure, (b) input and output matching 81
Figure 48. Schematic diagram and chip micrograph of the GaAs MPA 82
Figure 49. Measurement results of the GaAs MPA. (a) Gain and matching performance, (b) output power, power gain and PAE versus input power at 15 GHz... 83
Figure 50. Schematic diagrams of (a) the inverter, (b) shift register, (c) latch 85
Figure 51. Schematic diagram and chip micrograph of the GaAs 5-bit digital attenuator 86
Figure 52. Measurement results of the GaAs 5-bit digital attenuator: (a) insertion loss and matching performance in the reference state, (b) insertion loss for all 32 attenuation... 88
Figure 53. Schematic diagram and chip micrograph of the GaAs 4-bit digital phase shifter 89
Figure 54. Measurement results of the GaAs 4-bit digital phase shifter: (a) insertion loss and matching performance in the reference state, (b) phase shift for all 16 states, (c)... 91
Figure 55. Block diagram and chip micrograph of the GaAs 9-bit SPC 92
Figure 56. Schematic diagrams of (a) the inverter, (b) shift register, (c) latch 93
Figure 57. Schematic diagrams of (a) IVT, (b) OVT for controlling the digital attenuator and phase shifter, (c) OVT for Dout[이미지참조] 95
Figure 58. A unit cell of the drain mixer 96
Figure 59. Simulated gm' versus VDS at different VGS. The gate width of transistor is 2x50-μm[이미지참조] 96
Figure 60. Simulated gm' and CGS versus transistor gate width at VDS=0 V and VGS=0.6 V[이미지참조] 97
Figure 61. Schematic diagram of the balanced distributed drain mixer 98
Figure 62. VSWR and cut-off frequency of the input (a) and output (b) artificial T-lines versus the T-line length at different transistor sizes 100
Figure 63. Simulated large-signal return loo at the LO port 101
Figure 64. chip micrograph of the balanced distributed drain mixer 102
Figure 65. Measured conversion gain of the balanced distributed drain mixer: (a) conversion gain versus RF frequency at fIF=0.4 GHz, (b) conversion gain versus IF...[이미지참조] 103
Figure 66. Measured IF output power and conversion gain versus RF input power of the distributed drain mixers with fIF=0.4 GHz and fRF=10.4 GH[이미지참조] 104
Figure 67. Measured port isolation of the distributed drain mixers 105
Figure 68. Block diagram and chip micrograph of the GaAs multifunction (a) transmitter, (b) receiver 107
Figure 69. Measurement results of the GaAs multifunction transmitter in the reference state: (a) gain and matching performance, (b) output power and power gain versus input... 108
Figure 70. Attenuation performance of the GaAs multifunction transmitter: (a) gain in the 32 attenuation states, (b) RMS attenuation and parasitic phase errors 109
Figure 71. Phase shift performance of the GaAs multifunction transmitter: (a) phase shift in the 16 phase states, (b) RMS phase and parasitic amplitude errors 110
Figure 72. Measured gain, noise figure and matching performance of the GaAs multifunction receiver 111
Figure 73. Attenuation performance of the GaAs multifunction receiver: (a) gain in the 32 attenuation states, (b) RMS attenuation and parasitic phase errors 112
Figure 74. Phase shift performance of the GaAs multifunction receiver: (a) phase shift in the 16 phase states, (b) RMS phase and parasitic amplitude errors 113