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Title Page
Abstract
Contents
Chapter 1. Introduction 11
1.1. Motivation 11
1.2. Thesis organization 12
Chapter 2. Basics of ADC Architecture 13
2.1. ADC Architecture 13
2.1.1. Flash ADC 13
2.1.2. Pipelined ADC 14
2.1.3. SAR ADC 16
2.1.4. Areas of Application of ADC Architectures 17
2.2. Inefficiency of SAR conversion for bio-signals 18
Chapter 3. Concept of Selective Switching Technique 20
3.1. Previous Research for Input-Based SAR ADCs 20
3.2. Input Selective Switching Technique 22
3.2.1. Characteristics of Comparison Time in Comparator 23
3.2.2. Comparison Time Based Switching Skip 24
3.2.3. Input Selective Switching for Bio-Signals 25
3.3. Modified DAC Switching 27
3.3.1. Switching Energy of V㎝-based SAR ADCs 27
3.3.2. Modified DAC Switching 30
Chapter 4. Design of Selective Switching Technique 33
4.1. Architecture 33
4.2. Calibration Circuit 35
4.3. Comparator 36
4.4. Bootstrapped Switch 38
4.5. Digital Logic 40
Chapter 5. Simulation Results and Analysis 43
5.1. Lay out 43
5.2. Post simulation result and analysis 44
Chapter 6. Conclusions 46
6.1. Summary 46
6.2. Future work 46
Reference 48
Curriculum Vitae 50
Table 3.1. The number of bit cycle for each signals 26
Fig 1.1. General system block diagram for bio-medical application 11
Fig 2.1. Conventional 2-bit Flash ADC 14
Fig 2.2. Conventional N-bit pipelined ADC 15
Fig 2.3. Conventional SAR ADC 16
Fig 2.4. ADC area with resolution and sampling rate 17
Fig 2.5. Inefficiency of SAR switching for small input 18
Fig 3.1. SAR ADC with Bypass Window 21
Fig 3.2. LSB First Switching SAR ADC 22
Fig 3.3. Plots of comparison of comparator for each input 23
Fig 3.4. Comparison time for input voltage 24
Fig 3.5. Example of skipping phases for 4-bit SAR ADC 25
Fig 3.6. Signals and histograms of EEG, EMG, ECG 26
Fig 3.7. The switching energy of V㎝-based method for 4-bit 28
Fig 3.8. Example of direct switching for 4-bit 29
Fig 3.9. (a) energy of direct switching at each input code (b) V㎝-based switching energy in... 29
Fig 3.10. Comparison between direct switching and modified switching 30
Fig 3.11. (a) energy of modified switching in each phase (b) switching energy versus output... 31
Fig 3.12. Comparison of switching energy between switching method 32
Fig 4.1. The architecture of selective switching SAR ADC 34
Fig 4.2. Calibration using charge pump and voltage controlled delay 35
Fig 4.3. StrongARM latch comparator 36
Fig 4.4. (a) two-stage comparator (b) energy efficient two stage comparator (c) latch phase... 37
Fig 4.5. Modeling of sample switch 38
Fig 4.6. Operation of bootstrapped switch 39
Fig 4.7. Bootstrapped switch 40
Fig 4.8. FFT plot of bootstrapped switch 40
Fig 4.9. Operation of (a) shift REG and (b) bit REG 41
Fig 4.10. Modified digital logic for selective switching 42
Fig 5.1. Lay out of proposed design manufactured by 0.18um CMOS process 43
Fig 5.2. Post simulation results at input frequency of 25㎑ and 232㎑ 44
Fig 5.3. Results of power simulation depending on input magnitude 45
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