생몰정보
소속
직위
직업
활동분야
주기
서지
국회도서관 서비스 이용에 대한 안내를 해드립니다.
검색결과 (전체 1건)
원문 있는 자료 (1) 열기
원문 아이콘이 없는 경우 국회도서관 방문 시 책자로 이용 가능
목차보기더보기
Title page
ABSTRACT
Contents
I. Introduction 17
1.1 Motivation 17
1.2 Comparison of Electrical and Optical Interconnection 22
1.2.1 Signal Loss in Transmission Channel 22
1.2.2 Crosstalk in Parallel Transmission 26
1.2.3 Impedance Matching 30
1.2.4 Power Dissipation 31
1.3 Bidirectional Multi-Giga Bit Optical Data Link 33
1.4 Dissertation Outline 35
II. Multichannel Driver and Limiting Amplifier 37
2.1 Introduction 37
2.2 Crosstalk Issue in Multichannel Transmission 38
2.3 Multi-Giga Bit and Multichannel VCSEL Driver Design 41
2.3.1 Requirements of VCSEL Driver 41
2.3.2 Multi-Giga Bit and Multichannel Transmitter Design 41
2.3.2.1 Electrical Equivalent Circuit Model of VCSEL 43
2.3.2.2 Circuit Description and Simulaton Results 44
2.3.2.3 Measurements 54
2.3.3 Multichip Optical Transmitter Module Design 58
2.3.3.1 Introduction 58
2.3.3.2 Design and Integration 59
2.3.3.3 Measurements 65
2.4 Multi-Giga Bit and Multichannel Limiting Amplifier Design 68
2.4.1 Requirements of Limiting Amplifier 68
2.4.2 Circuit Description and Simulation Results 69
2.4.3 Measurements 73
2.5 Discussion and Summary 78
III. Bidirectional Transceiver Design 79
3.1 Introduction 79
3.2 Circuit Description and Simulation Results 80
3.3 Measurements 90
3.4 Discussion and Summary 96
IV. Bidirectional Optical Data Link 97
4.1 Demonstration of Bidirectional Optical Link Using Optical Fiber 97
4.2 Demonstration of Bidirectional Optical Link on OPCB 100
4.2.1 Overview 100
4.2.2 Electrical Signal Path 101
4.2.3 Fabrication and Characteristics of the OPCB 103
4.2.4 Optical Connector 104
4.2.5 Link Design and Components Assembly 106
4.2.6 Bidirectional Optical Link Test 109
4.3 Discussion and Summary 111
V. Conclusions and Future Works 112
5.1 Conclusions 112
5.2 Future Works 113
국문초록 115
References 118
Acknowledgement 125
Academic Experience 128
Table 1-1. Relative merits of electrical and optical interconnection technologies. 32
Table 2-1. Values of VCSEL electrical model parameters. 44
Table 2-2. Measured rise/fall times and peak-to-peak jitters of four-channel driver IC. 54
Table 2-3. Measured rise/fall times and peak-to-peak jitters of four-channel LA IC. 73
Figure 1-1. Transistor physical gate length trends : ITRS 17
Figure 1-2. ITRS roadmap : (a) on- and off-chip clock frequency and (b) number of chip I/O pins 19
Figure 1-3. A part of Intel chipset express block diagram 20
Figure 1-4. A three-state bidirectional output buffer. 21
Figure 1-5. Equivalent circuit model per unit length of transmission line. 23
Figure 1-6. Contributions to loss versus frequency for copper traces on FR-4 board 24
Figure 1-7. 3-dB bandwidth vs. interconnection length in electrical and optical interconnection. 25
Figure 1-8. Parallel trances over ground plane and its fundamental representation of crosstalk. 26
Figure 1-9. Frequency domain crosstalk between parallel microstrip lines. 28
Figure 1-10. Time domain crosstalk : (a) without crosstalk, (b) outside sources with clock-like pattern and central data line with PRBS pattern, (c) all PRBS pattern with same 29
Figure 1-11. Examples of waveform distortion due to impedance mismatch at memory slots. 31
Figure 1-12. Chip-to-chip optical interconnection : (a) conventional link and (b) bidirectionallink. 34
Figure 2-1. An optical interconnection scheme using driver IC and receiver IC. 38
Figure 2-2. Simulated crosstalk responses for bondwires and substrate coupling effect with/without guard ring between channels. 40
Figure 2-3. Block diagram for four-channel CMOS VCSEL driver IC. 42
Figure 2-4. (a) Electrical equivalent circuit for the used VCSEL diode and (b) fitting model parameter. 43
Figure 2-5. Modified Cherry-Hooper amplifier and small-signal equivalent circuit with half. 49
Figure 2-6. Equivalent circuit of Cherry-Hooper amplifier with half for calculation of thetransfer function. 50
Figure 2-7. Circuit schematic of unit channel of four-channel VCSEL driver. 52
Figure 2-8. Simulated (a) frequency response and (b) eye diagram at 8 Gb/s data rate. 53
Figure 2-9. (a) Chip photograph and (b) packaged VCSEL driver IC. 55
Figure 2-10. Frequency response: small-signal gain and crosstalk between adjacent channels. 56
Figure 2-11. Measured eye diagrams of four-channel VCSEL driver IC. (a), (c) and (e) are for single channel operation, (b), (d) and (f) are for all channel operation 57
Figure 2-12. Application and the hybrid integration structure of a bottom-emitting VCSEL and a CMOS driver IC. 59
Figure 2-13. Simplified circuit diagram of an individual driver. 60
Figure 2-14. (a) Equivalent lumped model of parallel bondwires and (b) simulated coupling effect for a lumped model and a model provided in ADS. 62
Figure 2-15. Hybrid integrated multichip module : (a) topview and (b) cross-sectional view. 64
Figure 2-16. Frequency responses at a flip-chip bonded (FCB) VCSEL on a CMOS driver and at wire bonded (WB) VCSEL to the CMOS driver IC. 66
Figure 2-17. Measured non-filtered optical eye diagrams at 5 Gb/s : (a) without adjacentcrosstalk and (b) with adjacent crosstalk. Horizontal : 50 ps/div. 67
Figure 2-18. Block diagram of four-channel CMOS optical receiver front end. 69
Figure 2-19. Circuit schematic of unit channel of four-channel LA IC. 71
Figure 2-20. Simulation results : (a) frequency and (b) transient responses. 72
Figure 2-21. Chip photograph for four-channel LA IC. 75
Figure 2-22. Measured frequency response of four-channel LA IC. 75
Figure 2-23. Measured eye diagrams of four-channel LA IC. (a), (c) and (e) are for single channel operation, (b), (d) and (f) are for all channel operation, (a) and 76
Figure 2-24. Output amplitude corresponding to input amplitude change. 77
Figure 2-25. Bit error rate versus data rate for single and all channels operations. 77
Figure 3-1. Architectural configuration for a bidirectional chip-to-chip optical link. 80
Figure 3-2. The block diagram of the proposed bidirectional CMOS transceiver. 81
Figure 3-3. Detailed circuit of a common gain stage. 82
Figure 3-4. The schematic diagram of the output stage. 86
Figure 3-5. Simulated isolation analysis between the disabled output and the enabled input corresponding to the Tx and Rx operating modes. 87
Figure 3-6. Simulated frequency responses : (a) Rx mode and (b) Tx mode. 88
Figure 3-7. Simulated transient responses : (a) Rx mode and (b) Tx mode. 89
Figure 3-8. Experimental setup for (a) frequency response and (b) transient response. 91
Figure 3-9. Chip photograph of the Bi-TRx. 92
Figure 3-10. Frequency response of each operation mode. 93
Figure 3-11. 2.5-Gb/s eye diagrams for the (a) Tx and (b) Rx operating modes. Horizontal scale : (a) 66.1 ps/div. and (b) 100 ps/div. Vertical scale : (a) 2.8 mV/div. 94
Figure 3-12. BER performances for (a) input amplitude of Tx mode and (b) input optical power of Rx mode. 95
Figure 4-1. Testboard for bidirectional optical link using optical multimode fiber. 98
Figure 4-2. Measured eye diagrams at 2.5 Gb/s with multimode fiber links : (a) the TRx1-to-TRx2 transmission and (b) the TRx2-to-TRx1 transmission. Horizontal scale 99
Figure 4-3. Optical link concept for bidirectional transmission on the OPCB. 100
Figure 4-4. Model for the three-dimensional analysis of electrical signal path simulation consisting of microstrip lines on the TRx module and main board, and hollow 101
Figure 4-5. Results for the three-dimensional analysis : (a) frequency and (b) transient responses. 102
Figure 4-6. (a) Fabrication process of the OPCB and cross-sectional views of (b) 1-layer and (c) 2-layer OPCBs. 104
Figure 4-7. Bending losses at various radii of 90 -bent curvature of the fiber and the fabricated connector. 105
Figure 4-8. (a) Photograph of the 1 12 channels and 90 -bent fibers connector and (b) cross sectionalview of the connector. 106
Figure 4-9. Design architecture of module-to-board link. 107
Figure 4-10. (a) The assembled TRx module and (b) alignment between the optical connector and PD/VCSEL devices in TRx-1 and TRx-2 modules. 108
Figure 4-11. Demonstrator for bidirectional optical link on OPCB. 109
Figure 4-12. Measured eye diagrams at 1.25 Gb/s on the optical PCB : (a) TRx1-to-TRx2 (b) TRx2-to-TRx1transmissions. 110
원문구축 및 2018년 이후 자료는 524호에서 직접 열람하십시요.
도서위치안내: / 서가번호:
우편복사 목록담기를 완료하였습니다.
* 표시는 필수사항 입니다.
* 주의: 국회도서관 이용자 모두에게 공유서재로 서비스 됩니다.
저장 되었습니다.
로그인을 하시려면 아이디와 비밀번호를 입력해주세요. 모바일 간편 열람증으로 입실한 경우 회원가입을 해야합니다.
공용 PC이므로 한번 더 로그인 해 주시기 바랍니다.
아이디 또는 비밀번호를 확인해주세요
