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Title page
Abstract
Contents
1. Introduction 15
1.1 Definition of Ranging Process 16
1.2 Pre-defined Ranging Algorithms 16
1.2.1 TOA Ranging 17
1.2.2 TDOA Ranging 18
1.2.3 SSR 19
1.2.4 NFER 20
1.2.5 AOA Ranging 20
1.2.6 Summary of Classical Ranging Algorithms 22
1.3 Consideration Factors for Ranging Process 22
1.4 Previous Researches 23
1.4.1 Published Papers 23
1.4.2 Patents 25
1.5 Proposed Ranging Algorithms and Systems 27
2. Efficient Low-Complexity Ranging Algorithm for Low-Rate UWB Systems 30
2.1 Motivation 30
2.2 Systems Configuration 31
2.3 Proposed Ranging Process 32
2.4 Analysis for the Performance Evaluation 38
2.4.1 Synchronization Error 38
2.4.2 Clock Frequency Offset between Two Devices 39
2.4.3 Clock Frequency Offset between Two Pulse Generators in Device A 41
2.4.4 Timing Jitter in Two Clock Pulse Generations 44
3. Design of the UWB Receiver for Fast Ranging 47
3.1 Proposed Preamble Structure 48
3.2 System Model 51
3.2.1 Hybrid DS-TH UWB Signaling 51
3.2.2 UWB Channel Model 52
3.2.3 Received Signal 52
3.3 Characteristics of the Proposed Preamble Format 53
3.4 Block Diagram of the Proposed Receiver Structure 55
3.4.1 Chip Synchronization 58
3.4.2 Frame Synchronization 59
3.4.3 Code Synchronization 60
3.4.4 Symbol Synchronization and Ranging Process 62
4. Conclusion 65
국문요약 67
References 69
감사의 글 72
Table 1.1 : Conventional ranging algorithms 22
Table 1.2 : Characteristics of averaging and correlation algorithm 24
Table 1.3 : Properties of TOA estimation with GML algorithm 25
Table 1.4 : Properties of TOA estimation with matched filtering and iterative threshold update schemes 25
Table 2.1 : Comparison with two alternative candidates for reparation of the clock frequency offset 41
Table 2.2 : Distance error with clock frequency offset in case of two systems with different frequency setup 44
Figure 1.1 : Two-way time transfer model 17
Figure 1.2 : TDOA and OWR : (A) TOA estimation (B) TDOA estimation 18
Figure 1.3 : AOA localization : (A) 2-D. model (B) 3-D. model 21
Figure 1.4 : TWR schemes with GML detection algorithms 24
Figure 1.5 : Scanning receiver structure for FAP receiver 26
Figure 1.6 : FAP detector circuitry : (A) receiver circuitry (B) correlator circuitry (C) threshold circuitry 28
Figure 2.1 : System configuration for ranging 32
Figure 2.2 : Ranging algorithm 33
Figure 2.3 : Illustration of ranging procedure including (A) packet exchange and (B) clock pulse flow chart in ranging mode 35
Figure 2.4 : SDS-TWR (indirect method) 40
Figure 2.5 : Offset tracking (direct method) 41
Figure 2.6 : Distance error with clock frequency offset (without frequency offset (0 ppm), one is allotted as f1=2.5126 MHz and f0=2.5000 MHz and the other is assigned as f1=2.5062 MHz and 43
Figure 2.7 : Effect of timing jitter on ranging accuracy 45
Figure 3.1 : Two possible ranging process : (A) without ranging protocol (B) with ranging protocol 47
Figure 3.2 : Proposed receiver structure for fast ranging 49
Figure 3.3 : Preamble structure for simultaneously conducting ranging and symbol synchronization process 50
Figure 3.4 : Effect of the spectral smoothness with TH and DS code : (A) spectrum of a PPM signal with TH sequence (B) 2-PPM signal spectrum using this TH sequence and DS sequence 54
Figure 3.5 : Total elapsed time for the proposed receiver to complete the ranging process with respect to the number of pico-net 55
Figure 3.6 : Receiver structure for fast ranging 57
Figure 3.7 : Block diagram for chip synchronization 58
Figure 3.8 : Block diagram for frame synchronization 59
Figure 3.9 : Block diagram for code synchronization 61
Figure 3.10 : Block diagram for symbol synchronization and ranging process 63
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