Title Page
Contents
ABSTRACT 21
CHAPTER 1. INTRODUCTION 25
1.1. Evolution of transistors 25
1.2. Highly purified semiconducting CNTs 26
1.3. Commercialization issues 28
1.4. Research motivation and dissertation outline 32
CHAPTER 2. WAFER-SCALE SEMICONDUCTING CONVENTIONAL CNT NETWORK TRANSISTORS 33
2.1. Introduction 33
2.2. Detailed fabrication process 35
2.3. Images of the fully fabricated CNT devices 40
2.4. Charge transport in semiconducting CNT networks 41
2.5. Temperature dependent semiconducting CNT networks 44
2.6. Drop casting and dipping method 49
2.7. Uniformity of the deposited CNT networks 51
2.8. Electrical characterization 53
CHAPTER 3. WAFER-SCALE CNT NETWORK TRANSISTORS FABRICATEED BY REUSING CNT SOLUTION FOR COMMERCIALIZATION 59
3.1. Introduction 59
3.2. Device fabrication process including reuse method 61
3.3. SEM images of the CNT networks deposited by reuse method 63
3.4. Electrical characterization 65
CHAPTER 4. WAFER-SCALE STRIPED CNT NETWORK TRANSISTORS FOR COMMERCIALIZATION 69
4.1. Introduction 69
4.2. Operational principle of striped CNT network 71
4.3. Device fabrication process 73
4.4. SEM images of the striped CNT network transistors 76
4.5. Structural parameters of the striped CNT devices 77
4.6. Electrical characterization 78
CHAPTER 5. WAFER-SCALE HYBRID CMOS LOGIC GATES AND PRACTICAL APPLICATIONS 84
5.1. Introduction 84
5.2. Device fabrication process of the hybrid CMOS logic gates 86
5.3. Performance of the hybrid complementary CMOS logic gates 88
5.4. Wafer-scale split-channel InGaZnO transistors 90
5.5. Nanoscale hybrid CMOS logic gates 95
5.6. Highly purified metallic CNTs 96
5.7. CNT floating gate memories 97
5.8. Transparent sensor applications 107
CHAPTER 6. CONCLUSION 111
REFERENCES 114
국문요약 128
Curriculum Vitae 131
Summary of Main Research Accomplishments 147
Table 2.1. Performance comparison for the solution-processed s-CNT network... 58
Table 4.1. Insights into proposed cost-effective methods such as dipping methods,... 83
Figure 1.1. Evolution of transistors with emerging materials and new... 25
Figure 1.2. Chirality map of CNTs, in which the m-CNTs and s-CNTs are denoted... 27
Figure 1.3. A DGU method by mixing the initially obtained CNT power with a... 27
Figure 1.4. Previously reported studies on single-walled CNT-based high-... 29
Figure 1.5. Previously reported studies on wafer-scale transistors and circuits based... 29
Figure 1.6. Techniques for n-type conversion in p-type CNT networks through... 30
Figure 1.7. Visually, a schematic diagram of commercialization in which... 31
Figure 2.1. Mask design for photolithography to integrate 8-inch wafer-scale CNT... 35
Figure 2.2. (I) Preparation of an 8-inch wafer covered with a SiO₂ layer with a... 36
Figure 2.3. Photographs and schematic diagrams of silanol groups introduced by O₂... 37
Figure 2.4. An amine layer acting as an effective adhesion layer for CNT network... 38
Figure 2.5. Photograph of pre-separated s-CNT solution in petri-dish and the... 39
Figure 2.6. Photograph and magnified top-view optical microscope images of 8-... 40
Figure 2.7. (a) CNTs with honeycomb network and cylindrical structures of sp²-... 41
Figure 2.8. Schematic diagram of a two-terminal CNT device and its electrical... 42
Figure 2.9. Illustration of different contributions to conductance in purified s-CNT... 43
Figure 2.10. SEM images of CNT networks with and without O₂ plasma treatment... 44
Figure 2.11. SEM images of CNT networks at various CNT deposition temperatures. 45
Figure 2.12. Transfer characteristics of CNT network transistors by deposition temperature. 46
Figure 2.13. Electrical parameters, such as ION, IOFF, SS, and ION/IOFF, of CNT...[이미지참조] 47
Figure 2.14. (a) CNT percolation network path and effective channel length (Leff)...[이미지참조] 48
Figure 2.15. Formation process of CNT network by drop casting method on amine-... 50
Figure 2.16. Process of forming uniform CNT networks by dipping method in an... 50
Figure 2.17. (a) AFM images of the CNT network channel based on a 99% s- CNT... 51
Figure 2.18. Average CNT network thickness and their distribution at top-left,... 52
Figure 2.19. (a) Transfer curves (-IDS-VGS) of CNT network transistors fabricated...[이미지참조] 53
Figure 2.20. Output characteristics (-IDS-VDS) of the CNT network transistor with...[이미지참조] 54
Figure 2.21. Summarized key performance parameters (ION x L/W, IOFF x L/W, log...[이미지참조] 55
Figure 2.22. Summarized main electrical variables of CNT network transistors... 56
Figure 2.23. Representative TLM plot of the Rtotal of the CNT network transistors as...[이미지참조] 57
Figure 3.1. Mixed m- and s-CNT channel-based transistors with very poor... 60
Figure 3.2. Schematic diagram of channel deposition by reusing s-CNT solution on... 62
Figure 3.3. SEM images of the CNT network channel in five wafers by reusing the... 64
Figure 3.4. The electrical transfer curves (-IDS-VGS) of the CNT network transistors...[이미지참조] 65
Figure 3.5. Output curves (-IDS-VDS) of the CNT network transistors with various...[이미지참조] 66
Figure 3.6. Summarized electrical performance parameters of 8-inch wafer-scale... 68
Figure 4.1. Reported stduides on techinques for improving device performance in... 70
Figure 4.2. Plot of conductance (σ) under conditions where CNT density (DCNT)...[이미지참조] 72
Figure 4.3. AFM images of the CNT network channel consisting of 99%, 95%, and... 74
Figure 4.4. Device schematic for the striped CNT network transistor constructed... 75
Figure 4.5. Top-view SEM images showing a single striped CNT network transistor... 76
Figure 4.6. Schematic diagram of a conventional (Nst=1) and striped (Nst>1) CNT...[이미지참조] 77
Figure 4.7. (a) Transfer characteristics (-IDS-VGS) and (b) key performance...[이미지참조] 79
Figure 4.8. Transfer characteristics (-IDS-VGS) and key performance parameters (ION,...[이미지참조] 80
Figure 4.9. Output characteristics (-IDS-VDS) of the conventional (Nst=1) and...[이미지참조] 80
Figure 4.10. Electrical characterization of the conventional 99% (Nst=1) and...[이미지참조] 82
Figure 5.1. Performance of p-type CNT and n-type IGZO transistors with controlled... 85
Figure 5.2. (I) Preparation of the starting Si wafer and deposition of a Ti local... 87
Figure 5.3. (a) A shematic diagram of a hybrid CMOS inverter consisting of p-type... 89
Figure 5.4. Photograph and magnified top view optical microscope images of an 8-... 91
Figure 5.5. (a) Transfer characteristics, (b) output characteristics of conventional... 93
Figure 5.6. Mask design and concept of nm-scale hybrid CMOS logic gates... 95
Figure 5.7. Pre-separated and highly purified m- and s-CNT solutions through the... 97
Figure 5.8. I. Preparation of a Si/SiO₂ substrate cleaned with O₂ plasma. II.... 98
Figure 5.9. (a) AFM images of FLGs constructed from a 99% m-CNT solution with... 100
Figure 5.10. Screeing effect of induced PFCs in high-κ oxides by m-CNT networks... 100
Figure 5.11. Simulated CNT FLGM structure to demonstrate the screening effect... 102
Figure 5.12. Memory switching characteristics (△VT-TPG or TER) at various VPG and...[이미지참조] 103
Figure 5.13. (a) Schematic cross-section of the channel length (L) direction of the... 105
Figure 5.14. Endurance and retention characteristics of the CNT FLGMs with the... 106
Figure 5.15. (a) A schematic showing a measurement system for an adjacent ERT... 108
Figure 5.16. (a) An image showing that a 99% m-CNT solution is spray coated on... 109
Figure 5.17. (a) A real ERT measurement image of a m-CNT/PDMS tactile sensor.... 110