Title Page
Abstract
Contents
Acronyms 16
Chapter 1. Introduction 19
1.1. Motivation and objectives 21
1.2. Thesis organization 21
1.3. Research contributions 23
1.3.1. The work conducted within the present thesis 23
1.3.2. Other contributions not directly related with this dissertation 25
Chapter 2. UWB technology overview and receiver structure 26
2.1. UWB technology overview 27
2.1.1. Definition and regulation of UWB technology 27
2.1.2. Features of UWB technology 28
2.1.3. Standardization and channel modeling of UWB technology 30
2.1.4. Signaling formats of UWB technology 31
2.1.5. Applications of UWB technology 32
2.1.6. Challenges in UWB technology 33
2.2. Rake receivers 35
2.2.1. Rake types 35
2.2.2. Rake combining schemes 37
2.3. Non-coherent receivers 37
2.3.1. Energy detectors (ED) 38
2.3.2. Transmitted reference (TR) receivers 39
2.4. Development of TR UWB technology 40
2.4.1. Variations to the original TR UWB system 40
2.4.2. Variations to the performance analysis of TR UWB systems 42
Chapter 3. A robust TR UWB AcR with the impact of GDR 45
3.1. Current studies related to the issues of a practical DL 46
3.2. Signal and system model 47
3.2.1. Transmit end 47
3.2.2. Channel model 48
3.2.3. Receive end 48
3.3. Performance analysis of an AcR with the impact of GDR 49
3.4. The statistical model of GDR and the effect of GDR on the system BER performance 52
3.5. An improved AcR with the impact of non-ideal DLs 54
3.6. Performance and discussions 57
3.7. Conclusions 59
Chapter 4. An improved TRPC scheme 61
4.1. Restraint of delay time for wideband DLs 62
4.2. Signal and system model 63
4.3. The impact of delay time on the TRPC system performance 65
4.4. An improved TRPC signaling structure 71
4.5. Performance analysis of iTRPC scheme 78
4.6. Simulation and numerical results 80
4.7. Conclusions 84
Chapter 5. A reconfigurable digital TRPC receiver design 86
5.1. Practical issues of an analog TR AcR 87
5.2. ADC technology for UWB sytems 88
5.3. A reconfigurable digital TRPC AcR 90
5.4. BEP performance analysis 96
5.5. Operational considerations of reconfigurable DL branches 99
5.6. Performance result and discussion 100
5.7. Implementations and complexity analysis 103
5.7.1. Complexity of synchronization 104
5.7.2. Complexity of demodulation and tracking 104
5.7.3. Complexity comparison among the reconfigurable TRPC receiver, the oTRPC receiver, and the conventional TR receiver 105
5.8. Conclusions 106
Chapter 6. An averaging TRPC digital receiver 112
6.1. Signal and system model 113
6.2. The averaging TRPC receiver and performance analysis 115
6.3. Simulation results and discussions 118
6.4. Conclusions 118
Chapter 7. Conclusions and future work 121
7.1. Conclusions 122
7.2. Future work 123
Bibliography 126
Table 2.1. Channel models for different propagation scenarios within the IEEE 802.15.3a. 31
Table 2.2. Channel models for different propagation scenarios within the IEEE 802.15.4a. 31
Table 5.1. The Comparison between analog and digital TR UWB receivers. 109
Table 5.2. Determining the optimum number of DL branches. 110
Table 5.3. Complexity for the synchronization implementation. 110
Table 5.4. Complexity for the demodulation and tracking process. 110
Table 5.5. Implementation complexity comparison between TRPC and TR receiver. 111
Fig. 1.1. Schematic overview of the topics covered within the present dissertation. 22
Fig. 2.1. FCC and ETSI UWB spectral masks for indoor devices. 29
Fig. 2.2. FCC and ETSI UWB spectral masks for outdoor devices. 29
Fig. 2.3. A non-coherent energy detector (ED) receiver structure. 38
Fig. 2.4. An example of the transmitted sequence of conventional TR scheme. 44
Fig. 2.5. A non-coherent transmitted reference (TR) receiver structure. 44
Fig. 3.1. (a) Auto-correlation receiver structure, (b) the TR signaling structure (not considering GDR effect). 49
Fig. 3.2. Three different GDRs with GDRR =1×10-11s.(이미지참조) 53
Fig. 3.3. BER performance degradation due to GDR under different SNR conditions 54
Fig. 3.4. Proposed autocorrelation receiver structure. 55
Fig. 3.5. BER performance comparison between conventional AcR and the proposed AcR with 4 DL branches. 58
Fig. 3.6. BER performance comparison between conventional AcR and the proposed AcR with 4DL branches under different SNR conditions. 59
Fig. 3.7. BER performance comparison for the proposed AcR with GDRR =1×10-10 s under different DL branch numbers.(이미지참조) 60
Fig. 4.1. Mean number of detectable paths when delay time belongs to [0,t] and the channel mode parameters in Table 2.1. 68
Fig. 4.2. Effect of Td on the BER performance of TRPC signaling under the 802.15.3a CM1 environment.(이미지참조) 69
Fig. 4.3. Effect of Td on the BER performance of TRPC signaling under the 802.15.3a CM1 environment.(이미지참조) 70
Fig. 4.4. Effect of Td on the BER performance of TRPC signaling under the 802.15.3a CM4 environment.(이미지참조) 71
Fig. 4.5. Effect of Td on the BER performance of TRPC signaling under the 802.15.3a CM4 environment.(이미지참조) 72
Fig. 4.6. The oTRPC signaling structure. 73
Fig. 4.7. The iTRPC signaling structure. 74
Fig. 4.9. The AcR structure. 77
Fig. 4.10. BEP performance comparison between iTRPC and oTRPC in IEEE 802.15.3a/4a channels. 81
Fig. 4.11. BEP performance comparison between oTRPC and iTRPC under IEEE802.15.3a CM1-CM4 channels. 82
Fig. 4.12. The effect of number of adding zeroes on the BEP performance of iTRPC under IEEE 802.15.3a CM1 channel. 83
Fig. 4.13. The effect of Td on the BEP of iTRPC scheme in CM1 channel.(이미지참조) 84
Fig. 4.14. The BEP performance of iTRPC scheme in CM1 channel with different number of DPCs and different number of adding zeros. 85
Fig. 5.1. Energy collection and the basic block diagram of the reconfigurable TRPC receiver. 90
Fig. 5.2. TRPC signal and its ACF with Nf = 6, bm =-1, and fsa=10㎓.(이미지참조) 94
Fig. 5.3. TRPC signal and its ACF with Nf = 6, bm =+1, and fsa=10㎓.(이미지참조) 95
Fig. 5.4. The optimum number of DL branches at SNR =16㏈ for different data rates. 101
Fig. 5.5. The effect of number of repeated DP pairs in one cluster on the TRPC performance under IEEE 802.15.3a (CM1 and CM4). 102
Fig. 5.6. BEP of the reconfigurable and the original TRPC AcR in CM4 channel model. 103
Fig. 5.7. Block diagram of the demodulation and tracking scheme. 107
Fig. 5.8. The total used number of resources for the TRPC (original/reconfigurable) and TR receiver (memory element, adder, and multiplier). 108
Fig. 6.1. The basic block diagram of the proposed averaging TRPC receiver. 114
Fig. 6.2. The BEP performance comparison between the original and the proposed averaging TRPC receiver with Nf=10.(이미지참조) 119
Fig. 6.3. The effect of Td and Rb on the BEP performance for both the original and proposed averaging TRPC receiver under IEEE 802.15.3a CM4 with Nf = 10 in each TRPC and 16㏈.(이미지참조) 120
Fig. 6.4. The effect of Td and Nf on the BEP performance for both the original and proposed averaging TRPC receiver under IEEE 802.15.3a CM1 with 5Mbps and 16㏈.(이미지참조) 120