표제지
초록
목차
제1장 서론 7
제2장 이론적 배경 13
2-1. 전자 패키지[20-25] 13
2-2. 전자패키지의 접속방법[26-29] 16
2-3. System in Package 20
제3장 실험방법 24
3-1. 비아 홀 시편의 제작 24
3-2. UBM의 형성 27
3-3. 가압주입법 28
3-4. 플립칩 본딩 32
제4장 결과 및 고찰 33
4-1. 압력에 따른 Sn의 주입 거동 33
4-2. 주입 시간에 따른 Sn의 주입거동 39
4-3. UBM 유무에 따른 Sn의 주입 거동 42
4-4. 비아 홀의 직경에 따른 Sn의 주입거동 47
4-5. 다른 크기의 비아들의 Sn 주입 52
4-6. 플립칩 본딩 55
제5장 결론 57
참고문헌 59
ABSTRACT 62
감사의 글 64
Table 2-1. Through hole package and Surface mount package. 15
Table 2-2. Properties with bonding methods. 19
Fig.1-1. (a) Schematic illustration and (b) SEM micrograph of a chip stack package processed using wire bonding 10
Fig.1-2. (a) Schematic illustration and (b) SEM micrograph of a chip stack package processed using Cu through-vias. 11
Fig.1-3. Process steps for a chip stack package using Cu through vias: (a) via hole formation, (b) Cu electroplating, (c) CMP & back-side grinding, (d) Cu/Sn bump formation, and (e)... 12
Fig.2-1. Schematic illustrations of (a) TAB Bonding, (b) Wire Bonding, (C) Flip Chip Bonding. 18
Fig.2-2. 3D stack interconnection for (a) Au wire bonding, (b) Cu vertical via. 22
Fig.2-3. Key technologies of 3D stacking. 23
Fig.3-1. SEM micrographs of the via hole patterns of (a) 200㎛ diameter, (b) 50㎛ diameter, and (c) 20㎛ diameter. 25
Fig.3-2. SEM micrographs of the via hole patterns of 200㎛, 50㎛, 20㎛, 10㎛ diameter. 26
Fig.3-3. The autoclave used for Sn via formation process using pressure infiltration of molten metal. 30
Fig.3-4. Schematic illustration of the autoclave used for Sn via formation process using pressure infiltration of molten metal. 31
Fig.4-1. SEM micrographs of the via holes of 50㎛ diameter filled with molten Sn by pressure infiltration method at a pressure of (a) 1 atm, (b) 2 atm, (c) 3 atm, (d) 5 atm, (e) 10 atm, (f) 20 atm,... 36
Fig.4-2. Schematic illustration of the via-hole volume (a) before and (b) after Sn infiltration (Vi is the initial via-hole volume and Vu is the unfilled via-hole volumes after Sn infiltration.) 37
Fig.4-3. Ratio of the unfilled via-hole volume after Sn infiltration to initial via-hole volume (Vu/Vi) vs. infiltration pressure (via-hole diameter: 50㎛).(이미지참조) 38
Fig.4-4. SEM micrographs of via-holes of 50㎛ diameter filled with molten Sn by pressure infiltration method at a pressure of 5atm for (a) 5 min and (b) 30 min. 40
Fig.4-5. Ratio of the unfilled via-hole volume after Sn infiltration to initial via-hole volume (Vu/Vi) vs. Sn infiltration time (via-hole diameter:50㎛).(이미지참조) 41
Fig.4-6. SEM micrographs of UBM-untreated via holes of 50㎛ diameter, filled with molten Sn by pressure infiltration method at a pressure of (a) 1 atm, (b) 3 atm, (c) 5... 44
Fig.4-7. Ratio of the unfilled via-hole volume after Sn infiltration to initial via-hole volume (Vu/Vi) vs. infiltration pressure (for UBM-treated and UBM-untreated via holes of 50㎛ diameter)(이미지참조) 45
Fig.4-8. SEM micrograph of a Sn through-via of 200㎛ diameter, taken out of an UBM-untreated via-hole during sonic process after wafer thinning. 46
Fig.4-9. SEM micrographs of the via holes of 20㎛ diameter, filled with molten Sn by pressure infiltration at a pressure of (a) 1 atm, (b) 5 atm, (c) 20 atm. 49
Fig.4-10. SEM micrographs of the via holes of 200㎛ diameter, filled with molten Sn by pressure infiltration at a pressure of (a) 1 atm, (b) 5 atm, (c) 20 atm. 50
Fig.4-11. Ratio of the unfilled via-hole volume after Sn infiltration to initial via-hole volume (Vu/Vi) vs. via-hole diameter.(이미지참조) 51
Fig.4-12. SEM micrograph of the trench vias of 50㎛ and 25㎛ width, filled with molten Sn by pressure infiltration at a pressure of 40 atm. 53
Fig.4-13. SEM micrograph of the via hole of 200㎛, 50㎛, 20㎛, and 10 ㎛ diameter. filled with molten Sn by pressure infiltration at a pressure of 40 atm. 54
Fig.4-14. SEM micrograph of a chip stack specimen formed by flip chip bonding of Sn through-vias with Sn solder bumps of Si substrate. 56