title page
ABSTRACT
Contents
1. INTRODUCTION 15
1.1. Motivation 17
1.2. Thesis outline 19
2. BURST-MODE RECEIVER ICs FUNDAMENTALs 22
2.1. Burst-mode transimpedance amplifier 23
2.1.1. TIA basic 23
2.1.2. Burst-mode TIA 25
2.2. Burst-mode limiting amplifier 26
2.2.1. Limiting amplifier basic 26
2.2.2. Burst-mode limiting amplifier 27
2.3. OLT receiver module 27
3. BURST-MODE RECEIVER FOR 1.25GB/s EPON WITH AGC AND INTERNALLY CREATED RESET SIGNAL 29
3.1. Introduction 29
3.2. General requirement for burst-mode receiver IC 30
3.3. Circuit design 31
3.3.1. TIA-AGC circuit 33
3.3.2. LA-AOC circuits 38
3.3.3. Reset creation circuit 39
3.3.4. LA with switch 47
3.3.5. Output buffer 49
3.4. Experimental results 50
3.5. Conclusion 56
4. BURST-MODE TIA FOR 1.25GB/s EPON WITH ANALOG AGC AND EXTERNAL RESET SIGNAL 60
4.1. Introduction 60
4.2. TIA core circuit 62
4.3. Burst-mode TIA block diagram 67
4.4. Top and bottom hold circuits 70
4.5. AGC and gain control circuit 71
4.6. Measurement results 72
4.7. Conclusion 78
5. BURST-MODE TIA WITH MULTI-LEVEL STEP AGC AND SELECTIVE INTERNALLY-CREATED RESET FOR 1.25GB/s EPON 82
5.1. Introduction 82
5.2. Target specification and design parameters 83
5.3. BM-TIA circuit design 86
5.3.1. AGC operation 88
5.3.2. Reset generation 89
5.3.3. Compact and self-calibrated design 93
5.4. Simulation and measurement result 94
5.5. Conclusion 98
6. CONCLUSION 101
ACKNOWLEDGEMENT 103
CURRICULUM VITAE 105
Table 3.1: Performance summary of BM-RX 55
Table 4.1: Performance summary of BM-TIA external reset 76
Table 5.1: Target of the BM-TIA design 84
Figure 1.1 : EPON system configuration 17
Figure 1.2 : EPON transmission 18
Figure 2.1 : Typical application of an optical receiver 22
Figure 2.2 : Basic TIA configuration 23
Figure 2.3 : Photodiode model 24
Figure 2.4 : TIA model including photodiode 24
Figure 2.5 : Typical limiting amplifier cell 27
Figure 2.6 : OLT receiver configuration (a) BM-TIA + CW-LA, (b) BMTIA+ BM-LA, (c) BM-RX 28
Figure 3.1 : Receiver block diagram 32
Figure 3.2 : TIA-AGC circuit 34
Figure 3.3 : TIA basic circuit 35
Figure 3.4 : (a) Top-hold (TH) and (b) bottom-hold (BH) circuits 36
Figure 3.5 : LA-AOC circuit 38
Figure 3.6 : (a) Reset timing and (b) Reset creation concept from BLE signal 41
Figure 3.7 : Reset creation circuit block diagram 42
Figure 3.8 : Simulated reset creation process (a) from high to low power bursts and (b) from low to high power bursts 43
Figure 3.9 : Bottom-level envelope (BLE) detector circuit 45
Figure 3.10 : LA-AOC with switch circuit 48
Figure 3.11 : Output buffer circuit 49
Figure 3.12 : Burst-mode test fixture 50
Figure 3.13 : Measured waveform concerning reset creation operation 51
Figure 3.14 : Measured waveforms at two outputs and anticipated reset signal 52
Figure 3.15 : BER measurement result 53
Figure 3.16 : Eye diagram of burst-mode receiver with 27-1 PRBS(이미지참조) 54
Figure 3.17/Figure 13.17 : Chip micrograph 0.9 x 1.9 mm2 includes all components 55
Figure 4.1 : EPON system 60
Figure 4.2 : Simplified block diagram of a) conventional TIA, and b) newly proposed TIA 62
Figure 4.3 : Simulated peak cancellation effect of C FB(이미지참조) 65
Figure 4.4 : Comparison between conventional and new feedback network 66
Figure 4.5 : The burst-mode TIA-AGC block diagram 67
Figure 4.6 : Waveform in burst-mode TIA 69
Figure 4.7 : Superdiode configuration for top-hold circuit 70
Figure 4.8 : AGC operation and dc level detection diagram 72
Figure 4.9 : AGC effect on the TIA-AGC gain, measured in continuous mode 73
Figure 4.10 : Frequency response of the burst-mode TIA at different input levels. 74
Figure 4.11 : Main TIA output and its detected dc level in typical burst-mode condition. Reset signal is not to scale 75
Figure 4.12 : Burst-mode eye diagram the burst-mode TIA circuit 77
Figure 4.13 : Die photograph, chip size 1.3 x 0.9 mm2, all components on-chip(이미지참조) 78
Figure 5.1 : OLT receiver module with BM-TIA with selective internal reset 82
Figure 5.2 : Summary of simulation target 85
Figure 5.3 : BM-TIA block diagram 86
Figure 5.4 : Waveform explaining AGC and reset generation operation 90
Figure 5.5 : Simulated noise performance of the BM-TIA 94
Figure 5.6 : Simulated frequency response of the BM-TIA 95
Figure 5.7 : Measured waveform of BM-TIA output with 26.5dB loud/soft ratio 97
Figure 5.8 : PIN-TIA assembly and typical eye diagram 98