title page
ABSTRACT
Contents
1. Introduction 15
1.1. Motivation 15
1.2. Dissertation Outline 17
2. Programmable LC Resonant Circuit 19
2.1. Review of Design Techniques for Multi-standard Component 19
2.2. Switched Capacitor Array and Switched Inductor Array 22
2.3. Concept and Applications of Programmable LC Resonant Circuit 24
2.4. Analysis of Programmable LC Resonant Circuit 30
2.5. Summary 34
References for Chapter 1 and 2 35
3. Basics of Differential LC Oscillator 37
3.1. Models for LC Oscillator 37
3.2. Differential LC Oscillator 39
3.3. Phase Noise Theory 43
References 53
4. Low Power Low Phase Noise Quadrature Generation Topology 55
4.1. Overview of Existing Quadrature Generation Methods 55
4.2. Cross Coupling and Super-harmonic Coupling 58
4.3. Proposed Low Power Low Phase Noise Quadrature Generation Method 64
4.4. Comparison of Proposed Topology with Existing Super-Harmonic Coupling Methods 66
4.5. Simulation Results 67
4.6. Summary 70
References 71
5. Design of Reconfigurable CMOS LC QVCO 73
5.1. Design Considerations 73
5.2. Design of LC Tank 74
5.3. Design of the VCO 78
5.4. Experimental Results 80
5.5. Analysis of Parasitic in Implementation 84
5.6. Designed QVCO as a Programmable Component 88
5.7. Revision on Schematic 95
5.8. Summary 102
References 102
6. Conclusions 103
[국문요약] 105
Acknowledgements 109
Curriculum Vitae 111
Table 2-1. The equations for the maximum and minimum values of tank reactance 30
Table 4-1. A comparison of the proposed QVCO against state-of-the-art QVCOs 70
Table 5-1. VCO performance requirements 74
Table 5-2. Summary of measurement result and comparison with simulation result 83
Table 5-3. Length and parameters of each interconnection line 87
Table 5-4. L, C values for each control signal and corresponding oscillation frequency 93
Table 5-5. L, C values for each control signal and corresponding oscillation frequency 101
Figure 1-1. WLAN, WCDMA and Wibro multi-standard receiver architecture 16
Figure 1-2. Signal processing in proposed receiver architecture… 16
Figure 2-1. Comparison of wide-band design and narrow-band design 20
Figure 2-2. Wide-band design technique (a) and concurrent design technique (b) 20
Figure 2-3. Tuning with an active inductor (a) and tuning with switched inductor (b) 21
Figure 2-4. Switched capacitor array 23
Figure 2-5. Switched inductor array 24
Figure 2-6. The equivalent model of switched inductor array… 24
Figure 2-7. Concept of programmable LC resonant circuit 25
Figure 2-8. Concept of conjugate matching 26
Figure 2-9. Programmable LC resonant circuit as a input matching network 26
Figure 2-10. Simple input impedance model of matching network including input transistor 27
Figure 2-11. Programmable LC resonant circuit as a LC tank 29
Figure 2-12. MOS transistor model from TSMC 0.18 um library[11] 31
Figure 2-13. A simple MOS switch model for analysis 31
Figure 2-14. Simpler model when drain node is grounded 32
Figure 2-15. MOS switch characteristics when on vs. the width of transistor… 32
Figure 2-16. MOS switch characteristics when off vs. the width of transistor… 33
Figure 2-17. Possible connections of switches with capacitance or inductance 34
Figure 3-1. Feedback model of oscillator 37
Figure 3-2. One port model… 38
Figure 3-3. Negative resistance generation circuit and its equivalent 39
Figure 3-4. Negative resistance oscillator… 41
Figure 3-5. Various implementations of CMOS differential LC oscillators… 42
Figure 3-6. Phase noise in frequency domain… 43
Figure 3-7. Reciprocal mixing 44
Figure 3-8. Effect of timing jitter in flip-flop 45
Figure 3-9. The noise model for resonator based negative resistance oscillator 47
Figure 3-10. Tank impedance 47
Figure 3-11. Phase noise description by Leeson's model 49
Figure 3-12. Concept of ISF (Impulse Sensitivity Function) 50
Figure 3-13. Phase noise representation and f1/3 corner frequency derived by Harjimiri(이미지참조) 50
Figure 3-14. Concept of phase noise mechanism In differential LC oscillator 51
Figure 3-15. Optimization of phase noise performance by noise filtering 53
Figure 4-1. Schematic of poly-phase filter 56
Figure 4-2. Cascaded poly-phase filter 56
Figure 4-3. Quadrature generation using master and slave flip-flop 57
Figure 4-4. Quadrature generation using four stage ring oscillator with feed-forward path 58
Figure 4-5. Cross coupled QVCO 59
Figure 4-6. Conceptual diagram of cross coupled QVCO 59
Figure 4-7. Modification of cross coupling quadrature generation topology [7-9] 60
Figure 4-8. Concept and MOS implementation of super-harmonic coupling 62
Figure 4-9. Super-harmonic coupled QVCOs without extra 2ω0 oscillator [11], [12](이미지참조) 63
Figure 4-10. Conceptual idea of super-harmonic coupling 65
Figure 4-11. Proposed QVCO topology 66
Figure 4-12. Phase noise performance comparison 69
Figure 4-13. Oscillation frequency and phase noise @1MHz vs. control voltage 70
Figure 5-1. TSMC spiral inductor and varactor models… 75
Figure 5-2. Series resistance to parallel resistance conversion 77
Figure 5-3. The schematic of reconfigurable LC tank (Half) 78
Figure 5-4. Full schematic of designed VCO 79
Figure 5-5. The variation of each performance parameter with the variation of coupling transistor size 79
Figure 5-6. The chip photo of designed VCO 81
Figure 5-7. The frequency tuning characteristics of the VCO at high operation frequency 81
Figure 5-8. The frequency tuning characteristics of the VCO at low operation frequency 82
Figure 5-9. Measured phase noise characteristics at 2.44 GHz 82
Figure 5-10. Quadrature operation of VCO 83
Figure 5-11. Phase noise performance at different tuning frequency and different frequency offsets 84
Figure 5-12. Interconnection lines between spiral inductors 85
Figure 5-13. Model for interconnection line 86
Figure 5-14. Phase noise simulation results at 2.4 GHz 87
Figure 5-15. Concept of programmable component 88
Figure 5-16. Conceptual diagram of programmable QVCO 89
Figure 5-17. The schematic of reconfigurable LC tank (Half) 90
Figure 5-18. Redrawn schematic of LC tank considering parasitic 91
Figure 5-19. Full schematic of designed VCO 96
Figure 5-20. Revision of schematic 98
Figure 5-21. Phase error vs. the width of core transistors 99
Figure 5-22. Expected inductor layout 100